Break the Loop

Verification Frameworks - Webinar

Join us on January 28th for our first webinar in 2026. You’ll learn how Sigasi’s shift-left approach saves you valuable time and money in verification. A must watch for design & verification engineers in both SystemVerilog and VHDL.

Verification Frameworks - Sigasi Visual HDL webinar

In this webinar you will learn how to (better) use your prefered verification methodology like:

UVM

The Universal Verification Methodology is an IEEE standard IEEE 1800.2-2020 and was originally created by Accelera in 2011. It is now further developed by the UVM Working Group . UVM has become the de facto standard for verification of ASIC designs (more than 75%) and is also heavily used in FPGA designs (almost 50%). We could not do a webinar on verification without UVM.

OSVVM

The Open Source VHDL Verification Methodology is one of VHDL’s answer to SystemVerilog’s UVM. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. OSVVM has grown fast between 2020 and 2024, and is now being used in 25% of ASIC designs and more than 30% in FPGA designs.

UVVM

The Universal VHDL Verification Methodology is the other answer. Originally developed by Espen Tallaksen and supported by the European Space Agency ESA it is a fast growing verification methodology. See also the Introduction to UVVM by CERN, one of our customers and partners. UVVM is now being used in more than 25% of ASIC designs and almost 30% of FPGA designs.

VUnit

VUnit is an open source unit testing framework for VHDL and SystemVerilog. The VUnit project was started by Lars Asplund and Olof Kraigher. VUnit complements traditional testing methodologies by supporting a “test early and often” approach through automation. VUnit automatically scans your HDL code for unit tests (aka test benches), runs them with your favorite simulator and reports the results. VUnit helps to run tests continuous and automated, and allows you to iterate faster. As of release 2025.3 VUnit is fully integrated in Sigasi Visual HDL.

More on VUnit Integration in Sigasi Visual HDL

Cocotb

The COroutine based CO-simulation Testbench environment for verifying VHDL and SystemVerilog RTL using Python encourages the same philosophy of design reuse and randomized testing as UVM. cocotb is now being used in 5% of ASIC designs and more than 20% of FPGA designs.

Remark: All adoption numbers are based on the 2024 Wilson Research Group IC/ASIC functional verification trend report and 2024 Wilson Research Group FPGA functional verification trend report

We broadcast our first Sigasi Visual HDL webinar in 2026 live on Wednesday 28th of January at 9:00AM CET/1:30PM IST/5:00PM JST and at 9:00AM PST/12PM EST/6PM CET.

Select your prefered time on the form below by clicking on the v and register now.

2025-12-02, last modified on 2025-12-15