Break the Loop

Verification Frameworks - Webinar

Join us on January 28th for our Verification Frameworks webinar

We call it also “Break the Loop” as you will learn how Sigasi’s shift-left approach can save you up to 20% of your time in verification and simulation. A must see for design & verification engineers in both SystemVerilog and VHDL.

Verification Frameworks - Sigasi Visual HDL webinar

You can learn more about Verification Frameworks in Sigasi for free from our experts. Sigasi Visual HDL supports the following open source verification methodologies:

UVM

The Universal Verification Methodology is an IEEE standard IEEE 1800.2-2020  and was originally created by Accelera in 2011. It is now further developed by the UVM Working Group . UVM has become the de facto standard for verification of ASIC designs (more than 75%) and is also heavily used in FPGA designs (almost 50%). More on UVM in Sigasi Visual HDL

OSVVM

The Open Source VHDL Verification Methodology is VHDL’s answer to SystemVerilog’s UVM. OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. OSVVM  has grown fast between 2020 and 2024, and is now being used in 25% of ASIC designs and more than 30% in FPGA designs. More on OSVVM in Sigasi Visual HDL

UVVM

The Universal VHDL Verification Methodology is another also a VHDL verification library and methodology. Originally developed by Espen Tallaksen and supported by the European Space Agency ESA it is a fast growing verification methodology. See also the Introduction to UVVM  by CERN, one of our customers). UVVM  is now being used in more than 25% of ASIC designs and almost than 30% in FPGA designs. More on UVVM in Sigasi Visual HDL

Cocotb

The COroutine based CO-simulation Testbench environment for verifying VHDL and SystemVerilog RTL using Python encourages the same philosophy of design reuse and randomized testing as UVM. cocotb  is now being used in 5% of ASIC designs and more than 20% of FPGA designs.

VUnit

VUnit is an open source unit testing framework for VHDL/SystemVerilog. The VUnit project was started by Lars Asplund and Olof Kraigher. VUnit  complements traditional testing methodologies by supporting a “test early and often” approach through automation. VUnit automatically scans your HDL code for unit tests (aka test benches), runs them with your favorite simulator and reports the results. VUnit helps to run tests continuous and automated, and allows you to iterate faster. More on VUnit in Sigasi Visual HDL

Remark: All adoption numbers are based on the 2024 Wilson Research Group IC/ASIC functional verification trend report and 2024 Wilson Research Group FPGA functional verification trend report

We broadcast our first Sigasi Visual HDL webinar in 2026 live on Wednesday 28th of January at 9:00AM CET/1:30PM IST/5:00PM JST and at 9:00AM PST/12PM EST/6PM CET. Select your prefered time on the form below and register now. You will learn how to (better) use your prefered verification methodology with Sigasi and save valuable time and money.

2025-12-02, last modified on 2025-12-03