Verification at the FPGA-Kongress in Munich

Our thoughts on the FPGA-Kongress 2016

Munich, Tuesday 12th - Thursday 14th of July

The focus of the FPGA - Congress is on user-friendly solutions that can be quickly integrated into your own development. Visitors have benefited from the FPGA knowledge of the top 50 speakers from all over Europe, the US, and Japan on 8 topics with more than 110 technical presentations and hands-on tutorials.

VHDL for Verification

This conference proved once again that VHDL for Verification is a viable alternative to SystemVerilog. Two notable speakers, Jim Lewis from SynthWorks and Espen Tallaksen from Bitvis, presented their industry tested verification methodologies (OSVVM and UVVM, respectively). Both these methodologies use libraries based on standard VHDL 2008 constructs, and constitute an alternative to the expensive and complicated UVM methodology that "Big EDA" is promoting.

The pictures

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fpga-kongress-2016-talk-2 fpga-kongress-2016-talk-1 
fpga-kongress-2016-talk-3 fpga-kongress-2016-talk-4