Contact us Start a Trial

Released on 2026-10-19

Sigasi Visual HDL 2026.5

Sigasi Visual HDL™ (SVH™) 2026.5 opens the Sigasi MCP server to all AI agents, including Claude Code, Codex, and Mistral Vibe, renders WaveDrom diagrams in hovers and documentation, adds spell checking for HDL comments, introduces project-specific dependency search paths for Modular Projects, and brings new VHDL declaration checks, along with several refinements and bug fixes.

MCP server for every AI agent

The Sigasi MCP server lets AI agents format HDL, read Sigasi’s real linting violations, and explore your project’s structure.

This functionality is now available to all agents running inside of VS Code: Claude Code, OpenAI Codex, Mistral Vibe, and others. The server keeps running inside the Sigasi extension, so the agent gets the same fast, project-aware analysis you see in your editor.

Registering an agent is a one-time action that can be triggered through the new MCP Registration Page. For each supported agent, the page shows the registration command, filled in with the location of the Sigasi MCP server on your machine. Copy it, or let Sigasi run it for you.
Learn more

The MCP server lives inside the extension. An editor must thus be open for an agent to connect to the server. For agents running where no editor is available, such as in CI, keep using the AI-ready Sigasi CLI.

WaveDrom diagrams

A picture says more than a thousand words, especially when it comes to timing. Sigasi 2026.5 renders WaveDrom  diagrams straight from your HDL comments. Describe your timing diagram, register bit-field, or logic circuit in a fenced code block tagged with the wavedrom identifier, and Sigasi renders the diagram in the hovers, the documentation live preview, and exported documentation.
Learn more

While the WaveJSON inside the comment is syntax highlighted and more support is planned, you can already let AI generate these descriptions to save precious time and ensure the documentation remains in sync with the implementation.

Spell checking

Typos in comments and strings tend to propagate and end up in artifacts such as generated documentation and code reviews. Sigasi 2026.5 integrates with the popular Code Spell Checker  extension. Once it is installed, Sigasi configures Code Spell Checker for Verilog, SystemVerilog, and VHDL files:

  • Only comments and string literals are checked, never identifiers or other code
  • Sigasi contributes dictionaries containing HDL keywords and common HDL vocabulary (testbench, bitstream, uart, etc.) to prevent most false positives
  • Comments in Sigasi’s project.sigasi and .sigasi/settings.json files are checked as well

Additional words can be added to your user or workspace dictionary through Code Spell Checker’s Quick Fix. All user configuration happens through the Code Spell Checker, not through Sigasi.
Learn more

Project dependency search path

Modular Projects resolve their dependencies through the dependency search path. Until now, that path could only be configured globally via the sigasi.dependencySearchPath setting and it only accepted absolute paths. Not ideal to share amongst projects or colleagues.

Sigasi 2026.5 adds a dependencySearchPath to the project description file, so that a checkout always works out of the box on any machine.

  • Paths may be either relative (resolved against the project’s root directory) or absolute.
  • Environment variables ($VAR, ${VAR}, ${VAR:default}) and ~ are expanded.
  • The project dependency search path has the highest priority and only applies to the project that defines it. It does not affect other projects.

This is especially useful for nested project setups, e.g., Git submodules. Simply add "." to the project search path, and every nested project is automatically found.
Learn more

VHDL declaration checks

This release resolves many long-standing customer requests in Sigasi’s VHDL validation. While all of the code below is also rejected by simulators, Sigasi now tells you about them one step earlier in the design process.

Subtype indications

VHDL Rules 264 to 269 validate subtype indications of signals, variables, constants, ports, generics, aliases, record and array elements, file types, and more. Most notably, unconstrained signals and variables are now reported, including partially constrained ones.
Learn more

Duplicate declarations

VHDL The existing duplicate declaration rule (54) now covers every declarative region. Newly detected duplicates include:

  • elements of a record
  • declarations in a package body that were already declared in the package
  • subprograms with the same signature
  • generic package, protected type, and subprogram instantiations, mode views, generics, subprogram parameters, physical units, and groups

The separate duplicate enum literal rule (69) is superseded by this rule, so you might see different problem markers after updating.
Learn more

Quality of life

Further new and noteworthy

  • The language server now starts in the background when no project is open, without checking out a license. This allows it to expose more functionality earlier and respond quicker to your requests
  • Reworked the quick picks for top level selection, UVM root component selection, Reveal in Target, Automate an Export with Task, and language mapping selection to be more consistent, complete, and user friendly
  • Removed the unnecessary Clear Top Level from the Command Palette. It remains available in the Design Hierarchy
  • Removed the none option when you already chose to include problem markers in Documentation Generation
  • Clarified the message of the file header comment linting rule. Note that this might break existing suppression comments
  • Verilog The begin/end template now shows up when typing begin
  • Verilog Removed the Set as Design Hierarchy Top code lens on nameless modules
  • Verilog Missing actuals for formals without a default value (rule 38) was upgraded to an error
  • VHDL Naming conventions are no longer checked on the ports of component declarations, as the entity declaration is already checked
  • VHDL Unary logical operators no longer require parentheses in VHDL-2019 files, e.g., bar <= and baz(1 downto 0) xor baz(2);
  • VHDL Added support for VHDL-2019 conditional expressions as actuals in generic maps, port maps, and subprogram calls without parentheses, e.g., G_VALUE => 0 when G_FLAG else 2

Bug fixes

  • Fixed invalid SonarQube output with empty rule ids in the CLI
  • Fixed links not opening in Cursor
  • Fixed missing refresh on the linting settings pages after editing .sigasi/settings.json
  • Fixed a crash in Documentation Generation on some state machines
  • Fixed block comments being rendered differently in documentation depending on their indentation
  • Fixed absolute hierarchical paths in the port actuals of a SystemVerilog bind targeting a VHDL entity or component instance, e.g., .rst(GTM.cls_i0.rst)
  • Fixed bind targets that match several design units only contributing the first match
  • Fixed Sigasi unresponsiveness during Documentation Generation and other tasks that touch many files
  • VHDL Fixed false positive sensitivity list warnings for aliases of record elements
  • VHDL Fixed Could not find declaration errors on index expressions in external names, e.g., << signal .tb.dut.gen(i).s : std_logic >>
  • VHDL Fixed false positive errors on calls to overloaded subprograms with named associations, e.g., OSVVM’s RandSlv(Size => 8, Exclude => (0 => x"01"))
  • VHDL Fixed false positive errors on unary operators and conditional expressions in VHDL-2019
  • VHDL Fixed missing component instantiations without port map, e.g., low_i : low;, in the Design Hierarchy
  • Verilog Fixed parse errors on parenthesized event expressions
    SYSTEMVERILOG 
      task t(input logic timer, active, clk);
    @(timer or active or (posedge clk iff active)); // Now parses
  endtask
  • Verilog Fixed operator precedence and operand binding in sequence, property, and event expressions:
    • a clocking event now covers the whole sequence instead of only its first term
    • always, eventually, accept_on, and friends are accepted as prefixes
    • not and nexttime bind to the correct operand
    • ## delays accept qualified and hierarchical names, e.g., ##pkg::C, ##cfg.N
    • &&& is accepted as a condition predicate without parentheses, e.g., a &&& b ? c : d
  • Verilog Fixed false positive errors for whitespace in repetition brackets, e.g., a[ *2 ], a[ -> 2 ]

Talkback

To allow us to analyze what features you use and in which way, we added Talkback reporting for

  • Net Search
  • Target settings pages, which were previously reported as folder settings

Talkback lets us find and fix bugs, steers our technical direction, and assists in feature prioritization. Talkback is only sent when the sigasi.enableTalkback setting is enabled.

Updates

  • Cursor MCP registration now requires executing a command, as shown in the MCP Registration Page.
  • Changes to the file header comment description might have broken comments suppressing the error
  • Verilog Linting rule 38 was updated to an error from a warning
  • VHDL Linting rule 69 has been superseded by 54

Update or install

If you have downloaded SVH from the VS Code Marketplace , your installation will automatically update. You can also download the latest .vsix file and manually install  it in VS Code.

The SHA sum is downloadable from https://download.sigasi.com/vs-code/updates/latest/vs-code-sha1.txt .

System requirements

Sigasi Visual HDL requires:

  • Windows 10 or Windows 11 64-bit
  • 64-bit Red Hat Enterprise Linux RHEL 8 or higher
  • VS Code >= 1.82 and < 2.0

We recommend having at least 8 GB of memory and about 1 GB of free disk space available for Sigasi Visual HDL.

Feedback

Our Support Team happily welcomes any of your feedback.