// STARC VHDL rules for Sigasi Visual HDL

{
    // case statement covers all cases
    "vhdl.rules.11.severity": "ERROR",
    "vhdl.rules.11.prefix": "STARC 2.2.1.1: ",
    // always use `others` in case statement
    "vhdl.rules.13.severity": "ERROR",
    "vhdl.rules.13.prefix": "STARC 2.8.1.4: ",
    "vhdl.rules.13.parameters.style": "ALWAYS_REQUIRE_OTHERS_CHOICE",
    // warn for duplicates in case statement
    "vhdl.rules.14.severity": "WARNING",
    "vhdl.rules.14.prefix": "STARC 2.8.1.3: ",
    // completeness of sensitivity list
    "vhdl.rules.72.severity": "ERROR",
    "vhdl.rules.72.prefix": "STARC 2.2.2.1: ",
    // no duplicates in sensitivity list
    "vhdl.rules.73.severity": "WARNING",
    "vhdl.rules.73.prefix": "STARC 2.2.2.2: ",
    // 2.2.2.4: further sensitivity list checks
    "vhdl.rules.38.severity": "WARNING",
    "vhdl.rules.38.prefix": "STARC 2.2.2.4: ",
    "vhdl.rules.39.severity": "ERROR",
    "vhdl.rules.39.prefix": "STARC 2.2.2.4: ",
    "vhdl.rules.85.severity": "WARNING",
    "vhdl.rules.85.prefix": "STARC 2.2.2.4: ",
    "vhdl.rules.197.severity": "ERROR",
    "vhdl.rules.197.prefix": "STARC 2.2.2.4: ",
    // find dead code
    "vhdl.rules.79.severity": "WARNING",
    "vhdl.rules.79.prefix": "STARC 2.7.2.2: ",
    // 1.1.1.6: entity - component match
    "vhdl.rules.90.severity": "WARNING",
    "vhdl.rules.90.prefix": "STARC 1.1.1.6: ",
    // naming conventions
    // TODO: you may want to alter some of the naming rules to match your company/team style
    "vhdl.rules.92.severity": "WARNING",
    "vhdl.rules.92.prefix": "STARC 1.1.1.2+: ",
    // file name ending in .vhd
    "vhdl.rules.92.parameters.file_name": {
        "valid": "[a-zA-Z]\\w+\\.vhd",
        "invalid": ""
    },
    // entity name (1.1.2.1) : min 2, max 32 characters (16 recommended, particularly for top level (1.1.1.9))
    "vhdl.rules.92.parameters.entity_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // 1.1.6.[1,2,3] architecture name
    "vhdl.rules.92.parameters.architecture_name": {
        "valid": "RTL|BEH|SIM|TB",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // No specific STARC rule for package names, in line with 1.1.2.1 for entities
    "vhdl.rules.92.parameters.package_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // No specific STARC rule for generics names, in line with 1.1.2.4 for constants
    "vhdl.rules.92.parameters.generic_name": {
        "valid": "[CP]_[A-Z0-9]{1,37}",
        "invalid": ""
    },
    // 1.1.2.5, 1.1.3.1: port names
    "vhdl.rules.92.parameters.port_name": {
        "valid": "\\w{2,40}",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "vhdl.rules.92.parameters.input_port_name": {
        "valid": "i_\\w*",
        "invalid": ""
    },
    "vhdl.rules.92.parameters.output_port_name": {
        "valid": "o_\\w*",
        "invalid": ""
    },
    "vhdl.rules.92.parameters.inout_port_name": {
        "valid": "io_\\w*",
        "invalid": ""
    },
    // 1.1.2.4 constant names
    "vhdl.rules.92.parameters.constant_name": {
        "valid": "[CP]_[A-Z0-9]{1,37}",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.variable_name": {
        "valid": "v_\\w{1,38}",
        "invalid": ""
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.signal_name": {
        "valid": "sig_\\w{1,36}",
        "invalid": ""
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.function_name": {
        "valid": "f_\\w{1,38}",
        "invalid": ""
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.procedure_name": {
        "valid": "p_\\w{1,38}",
        "invalid": ""
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.type_name": {
        "valid": "t_\\w{1,38}",
        "invalid": ""
    },
    // 1.1.2.5: signal, variable, type, label, function name: 2..40 characters (24 recommended)
    "vhdl.rules.92.parameters.label": {
        "valid": "\\w{1,40}",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // instance name (1.1.2.1) : min 2, max 32 characters
    "vhdl.rules.92.parameters.instantiation_statement_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },

    // 3.1.2.5: max line length
    "vhdl.rules.97.severity": "WARNING",
    "vhdl.rules.97.parameters.max_line_length": 110,
    "vhdl.rules.97.prefix": "STARC 3.1.2.5: ",
    // 3.1.4.3: use spaces for indentation
    "vhdl.rules.99.severity": "WARNING",
    "vhdl.rules.99.prefix": "STARC 3.1.4.3: ",
    // match port width and signal width
    "vhdl.rules.144.severity": "ERROR",
    "vhdl.rules.144.prefix": "STARC 3.2.3.2: ",
    // enforce consistent use of upper/lowercase
    "vhdl.rules.163.severity": "ERROR",
    "vhdl.rules.163.prefix": "STARC 1.1.1.5: ",
    // use named associations
    "vhdl.rules.164.severity": "ERROR",
    "vhdl.rules.164.prefix": "STARC 3.2.3.1: ",
    // use a standardized file header
    // TODO need to override with your company or team standard and remove the invalid pattern
    "vhdl.rules.188.severity": "INFO",
    "vhdl.rules.188.prefix": "STARC 3.5.3.3: ",
    "vhdl.rules.188.parameters.comment_header": {
        "valid": "Please configure the file header comment pattern",
        "invalid": ""
    },
    // 1.1.1.1/3.5.2.2: file name includes entity name
    "vhdl.rules.189.severity": "WARNING",
    "vhdl.rules.189.prefix": "STARC 1.1.1.1: ",
    // 1.1.1.3: no not use SystemVerilog reserved keywords
    "vhdl.rules.192.severity": "ERROR",
    "vhdl.rules.192.prefix": "STARC 1.1.1.3: ",
    // 2.1.6.1: use downto for 1D arrays
    "vhdl.rules.211.severity": "WARNING",
    "vhdl.rules.211.prefix": "STARC 2.1.6.1: ",
    "vhdl.rules.241.severity": "WARNING",
    "vhdl.rules.241.prefix": "STARC 2.1.6.1: ",
    // 2.10.3.1: vector size in comparison must match
    "vhdl.rules.232.severity": "ERROR",
    "vhdl.rules.232.prefix": "STARC 2.10.3.1: ",
    // 3.2.2.1: declare constants as constants
    "vhdl.rules.235.severity": "WARNING",
    "vhdl.rules.235.prefix": "STARC 3.2.2.1: ",
    // 2.1.2.3: specify integer range
    "vhdl.rules.236.severity": "ERROR",
    "vhdl.rules.236.prefix": "STARC 2.1.2.3: ",
    // 2.3.6.1: reset consistency
    "vhdl.rules.238.severity": "WARNING",
    "vhdl.rules.238.prefix": "STARC 2.3.6.1: ",
    // 2.7.3.1: limit nesting depth
    "vhdl.rules.239.severity": "WARNING",
    "vhdl.rules.239.prefix": "STARC 2.7.3.1: ",
    // 1.1.6.4: architecture in same file as its entity
    "vhdl.rules.243.severity": "WARNING",
    "vhdl.rules.243.prefix": "STARC 1.1.6.4: ",
    "vhdl.rules.243.parameters.multiple_architectures": "SAME_FILE_AS_PRIMARY",
    // 2.1.9.x: use of attributes
    "vhdl.rules.244.severity": "ERROR",
    "vhdl.rules.244.prefix": "STARC 2.1.9.x: ",
    "vhdl.rules.244.parameters.check_mode": "ALLOW",
    "vhdl.rules.244.parameters.attributes": [
        "range",
        "length",
        "left",
        "right",
        "high",
        "low",
        "reverse_range"
    ],
    "vhdl.rules.244.parameters.user_attributes": true,
    // 2.1.10.x, 2.9.3.1, 2.1.8.8: prohibited keywords
    "vhdl.rules.245.severity": "WARNING",
    "vhdl.rules.245.prefix": "STARC 2.1.10.x+: ",
    "vhdl.rules.245.parameters.keywords_and_operators": [
        "block",
        "alias",
        "bus",
        "register",
        "disconnect",
        "waveform",
        "record",
        "while",
        "procedure",
        "configuration",
        "exit",
        "next",
        "access"
    ],
    // 2.1.10.8+: forbidden pragmas
    "vhdl.rules.247.severity": "WARNING",
    "vhdl.rules.247.prefix": "STARC 2.1.10.8+: ",
    "vhdl.rules.247.parameters.pragmas": [
        "synopsys"
    ],
    // 1.4.3.4/3.3.3.1/3.3.6.1 clock and reset rules
    "vhdl.rules.249.severity": "ERROR",
    "vhdl.rules.249.prefix": "STARC 1.4.3.4/3.3.3.1/3.3.6.1: ",
    // 1.3.1.6/1.4.3.1/1.4.3.6/2.3.1.2
    "vhdl.rules.250.severity": "ERROR",
    "vhdl.rules.250.prefix": "STARC 1.3.1.6/1.4.3.1/1.4.3.6/2.3.1.2: ",
    "vhdl.rules.252.severity": "ERROR",
    "vhdl.rules.252.prefix": "STARC D1.3.1.6/1.4.3.1/1.4.3.6/2.3.1.2R4: ",
    "vhdl.rules.254.severity": "ERROR",
    "vhdl.rules.254.prefix": "STARC 1.3.1.6/1.4.3.1/1.4.3.6/2.3.1.2: ",
    // 3.1.3.4: one signal per line
    "vhdl.rules.253.severity": "WARNING",
    "vhdl.rules.253.prefix": "STARC 3.1.3.4: "
}