{
    // 1.1.1.x/1.1.2.x/3.1.2.1: naming conventions
    // TODO: you may want to alter some of the naming rules to match your company/team style
    "verilog.rules.2.severity": "ERROR",
    "verilog.rules.2.prefix": "STARC 1.1.1.x/1.1.2.x: ",
    "verilog.rules.2.parameters.macro_name": {
        "valid": "",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // 1.1.2.1: module name: max 32 characters (16 recommended)
    "verilog.rules.2.parameters.module_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.instantiation": {
        "valid": "",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // Use similar rules for other names
    "verilog.rules.2.parameters.interface_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.package_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.parameter_type_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.typedef_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.class_name": {
        "valid": "[a-zA-Z]\\w{1,30}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // 1.1.2.5: port & internal signal names
    "verilog.rules.2.parameters.port_name": {
        "valid": "",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.input_name": {
        "valid": "[a-zA-Z]\\w{1,28}_i",
        "invalid": ""
    },
    "verilog.rules.2.parameters.output_name": {
        "valid": "[a-zA-Z]\\w{1,28}_o",
        "invalid": ""
    },
    "verilog.rules.2.parameters.inout_name": {
        "valid": "[a-zA-Z]\\w{1,27}_io",
        "invalid": ""
    },
    "verilog.rules.2.parameters.net_name": {
        "valid": "[vns]_\\w{2,30}",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    "verilog.rules.2.parameters.var_name": {
        "valid": "[vns]_\\w{2,30}",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },
    // 1.1.4.2: parameter names: suggested prefix P_
    "verilog.rules.2.parameters.parameter_name": {
        "valid": "[pP]_\\w{1,29}[a-zA-Z0-9]",
        "invalid": "([Vv][Dd][Dd]|[Vv][Ss][Ss]|[Vv][Cc][Cc]|[Gg][Nn][Dd]|[Vv][Rr][Ee][Ff]).*|.*__.*"
    },

    // 1.1.1.3: Don't use VHDL keywords
    "verilog.rules.7.severity": "ERROR",
    "verilog.rules.7.prefix": "STARC 1.1.1.3: ",
    // 2.2.1.1: case statement must cover all cases
    "verilog.rules.8.severity": "ERROR",
    "verilog.rules.8.prefix": "STARC 2.2.1.1: ",
    // 1.1.1.1: file name must match module name
    "verilog.rules.17.severity": "WARNING",
    "verilog.rules.17.prefix": "STARC 1.1.1.1: ",
    // 3.1.5.3: default value for parameters
    "verilog.rules.19.severity": "WARNING",
    "verilog.rules.19.prefix": "STARC 3.1.5.3: ",
    // 3.1.4.5: line length
    "verilog.rules.20.severity": "INFO",
    "verilog.rules.20.prefix": "STARC 3.1.4.5: ",
    "verilog.rules.20.parameters.max_line_length": 110,
    // 3.1.4.3: use spaces for indentation
    "verilog.rules.21.severity": "WARNING",
    "verilog.rules.21.prefix": "STARC 3.1.4.3: ",
    // 3.5.3.x: use a standardized file header
    // TODO need to override with your company or team standard and remove the invalid pattern
    "verilog.rules.22.severity": "WARNING",
    "verilog.rules.22.prefix": "STARC 3.5.3.x: ",
    "verilog.rules.22.parameters.comment_header": {
        "valid": "Please configure the file header comment pattern",
        "invalid": ""
    },
    // 3.2.3.1: use name binding for instances
    "verilog.rules.24.prefix": "STARC 3.2.3.1: ",
    "verilog.rules.24.severity": "ERROR",
    // 2.8.1.4/2.8.3.5: one default clause required at end of case statement
    "verilog.rules.15.severity": "ERROR",
    "verilog.rules.15.prefix": "STARC 2.8.1.4/2.8.3.5: ",
    "verilog.rules.16.severity": "ERROR",
    "verilog.rules.16.prefix": "STARC 2.8.1.4/2.8.3.5: ",
    "verilog.rules.40.severity": "ERROR",
    "verilog.rules.40.prefix": "STARC 2.8.1.4/2.8.3.5: ",
    // 2.1.2.2: no non-blocking assignments in functions
    "verilog.rules.41.severity": "ERROR",
    "verilog.rules.41.prefix": "STARC 2.8.1.4/2.8.3.5: ",
    // 3.1.4.4: one statement per line
    "verilog.rules.47.severity": "INFO",
    "verilog.rules.47.prefix": "STARC 3.1.4.4: ",
    // 2.1.4.5/2.1.5.3/2.10.2.2: avoid logical operands to logic (1-bit) operators
    "verilog.rules.144.severity": "WARNING",
    "verilog.rules.144.prefix": "STARC 2.1.4.5/2.1.5.3/2.10.2.2: ",
    // 2.2.2.2: duplicate signal in sensitivity list
    "verilog.rules.160.severity": "WARNING",
    "verilog.rules.160.prefix": "STARC 2.2.2.2: ",
    // 3.1.3.1: port list ordering
    "verilog.rules.163.severity": "WARNING",
    "verilog.rules.163.prefix": "STARC 3.1.3.1: ",
    // 1.1.1.5: names should not be distinguished by upper/lowercase only
    "verilog.rules.166.severity": "WARNING",
    "verilog.rules.166.prefix": "STARC 1.1.1.5: ",
    // 2.7.3.1: limit nesting depth
    "verilog.rules.167.severity": "WARNING",
    "verilog.rules.167.prefix": "STARC 2.7.3.1: ",
    "verilog.rules.167.parameters.limit": 7
}