The Sigasi Software Development Kit (Sigasi SDK) enables all EDA tools to offer a modern editing experience for Verilog, SystemVerilog, and VHDL to their end users.
Every hardware design and verification engineer deserves an intelligent, fast, and super-responsive editor experience. Sigasi has been building a unique expertise with its Sigasi Studio IDE since 2008 and can now offer its features to other EDA tools with the Sigasi SDK.
Why do I need Sigasi SDK?
Digital hardware design is quite a challenge. No EDA toolchain or methodology is ever limited to 1 tool or 1 vendor. Engineers expect editors to be efficient, easy-to-use, fast, responsive, and have a very intuitive interface. There is no time for a learning curve when you have to switch tools.
Sigasi is in a unique position to offer you and your users the best-in-class experience as a benchmark for modern editors. Hardware engineers need all the support they can get to focus on the most important part of their job: creative design.
Sigasi’s features have been tested, improved upon, and expanded for more than a decade now by a team of engineers that only has a single mission: “Redefine Digital Design”. We have implemented best practices from every industry that works with hardware design and verification. On top of that, we have integrated lessons from various software industries and have served customers worldwide with Sigasi features for VHDL, Verilog, and SystemVerilog.
Based on the Language Server Protocol, Sigasi’s core technology is now available as an SDK to add extra power to other HDL tools. We consider this a new standard for modern IDEs.
How can my EDA tool integrate with Sigasi SDK?
The Sigasi Language Server runs in the background and provides feedback about HDL code when requested.
Which Sigasi features are available?
The Sigasi language server analyses source files in the background. Based on this analysis it can:
- Detect problems in the code
- While you type
- Exactly where the problems occur
- Even when there are multiple problems at once
- Offer smart, context sensitive autocomplete
- Calculate code folding ranges
- Provide hovers (tooltips) with more information about the code
- Provide the declaration location of identifiers (“Go to definition”)
- Find references to any declaration
- Calculate semantic highlighting information
- Automatically improve the formatting (“beautify”) of source files (and selections)
- Automatically rename identifiers project wide
- Provide an overview of the structure (outline) of the current file
- Provide the hierarchy of a design based on a top level
- Show the entire SystemVerilog file after expansion by the preprocessor
- Offer the ability to search for a specific VHDL or SystemVerilog design unit in the project
- + more to come
All or nothing solution? Not at all. You can pick and choose the features you want. You can even adopt Sigasi features one by one, if you prefer.
Sigasi SDK is written in Java and runs as a separate process. So it will never slow down your editor’s responsiveness.
What value can the Sigasi SDK bring to my EDA tool?
We know from user studies that, if you don’t deliver … in about 100 milliseconds, people start to get irritated: ‘The tool is too slow. I’m not going to use it any more’
A compiler that works on a finished program makes the core operating assumption that everything is correct. In an editor, your core operating assumption has to be the exact reverse. Whenever the user is typing something, his code is probably broken right now. He is in the middle of typing. He is not done.
Over the last decade we’ve become very accustomed to IDEs and powerful editors. … All of that stuff underneath the covers is powered by compilers. But a modern compiler is a very different compiler…