Advanced VHDL Configurations: Tying a component to an unrelated entity

Thu, 22 Mar 2012 00:00:00 +0000

Usually, people use VHDL configurations to select a given architecture for their component, or even to set generics that were not set in the instantiation. But you can also do more advanced stuff with configurations: you can tie a component to a completely unrelated entity. You can even re-wire the signals!

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Advanced VHDL Configurations: Tying a component to an unrelated entity