Altera on Sigasi

Importing a Quartus project in Sigasi Visual HDL

Fri, 30 Mar 2018 00:00:00 +0000

For some time it has been possible to integrate Sigasi Visual HDL (SVH) in Altera Quartus. Through feedback from our users, we have seen that this approach is good when starting a project or taking off with SVH on an existing Altera Quartus project. However, as a project grows and when more of the development work happens in SVH, keeping the link to the Altera Quartus project often gets in the way. Switching to a separate SVH project is more flexible. For example, this allows to show the source files in a hierarchical way in the Project Explorer.

Opening VHDL files in Sigasi, using Quartus

Wed, 19 Dec 2012 00:00:00 +0000

This page deals with step three of using the Quartus integration plugin for Sigasi. We assume have already set up Sigasi as default editor in Intel Quartus.

How to open an HDL file in Quartus

Step three happens when you open a VHDL file in Quartus, and Sigasi kicks in to show you the file. There are several ways to open an HDL file in Quartus. The most common ways are: you can double-click a file in the Quartus project navigator, or double-click an error in the console log.

VHDL Physical Type is not Synthesizable, or is it? (part 2)

Mon, 15 Oct 2012 00:00:00 +0000

In a previous post, VHDL Physical Type is not Synthesizable, or is it?, I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that the synthesis tool does not really have to deal with physical types at all.

VHDL Physical Type is not Synthesizable, or is it?

Thu, 11 Oct 2012 00:00:00 +0000

Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following “wisdom”:

Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]

List of known VHDL metacomment pragma's

Thu, 28 Apr 2011 00:00:00 +0000

Following up on a previous post, VHDL Pragmas, this is an incomplete list of supported VHDL pragmas, organized by vendor.

As an introduction, most pragmas have the following structure:

VHDL

-- trigger directive

where trigger is a keyword such as pragma or synthesis, and the directive is a special compiler directive. Many tools support several triggers, each with identical meaning.