<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Assert on Sigasi</title><link>https://www.sigasi.com/tags/assert/</link><description>Recent content in Assert on Sigasi</description><generator>Hugo</generator><language>en</language><lastBuildDate>Tue, 22 Sep 2009 00:00:00 +0000</lastBuildDate><atom:link href="https://www.sigasi.com/tags/assert/index.xml" rel="self" type="application/rss+xml"/><item><title>On HDL language design and library design</title><link>https://www.sigasi.com/tech/hdl-language-design-and-library-design/</link><pubDate>Tue, 22 Sep 2009 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/tech/hdl-language-design-and-library-design/</guid><description>&lt;h2 
 class="uk-heading-large" 
 id="assertions-and-constrained-random"&gt;
 &lt;a
 href="https://www.sigasi.com/tech/hdl-language-design-and-library-design/#assertions-and-constrained-random"
 class="uk-link-reset"
 aria-label="Link to this section: Assertions and constrained random"&gt;
 Assertions and constrained random
 &lt;/a&gt;
&lt;/h2&gt;
&lt;p&gt;Last week, I went to the closing symposium of the &lt;strong&gt;SoC Verification&lt;/strong&gt; project, where I was invited to talk about the Code Review process for hardware designers.&lt;/p&gt;</description></item></channel></rss>