Best Practices on Sigasi

Enabling DO-254 guideline checks in Sigasi SVH

Mon, 09 Feb 2026 00:00:00 +0000

DO-254 (also known as ED-80, “Design Assurance Guidance for Airborne Electronic Hardware”) is the primary international guidance used for developing complex, safety-critical electronic hardware for civil aircraft. It was jointly developed by RTCA (US) and EUROCAE (EU). First published in 2000, DO-254 became widely adopted in the avionics industry after the FAA accepted it as a means of compliance for avionics design assurance.

Enabling STARC rules in Sigasi SVH

Tue, 27 Jan 2026 00:00:00 +0000

STARC — the Semiconductor Technology Academic Research Center — was a research consortium established by leading Japanese semiconductor companies. Back in 2006, it released the STARC RTL Design Style Guides, a comprehensive collection of rules, recommendations, and best practices for RTL design. The guides cover everything from design creation and code management to verification workflows and general project organization, with separate volumes for Verilog/SystemVerilog and VHDL.

Use Case: Minimal Classic Project Setup

Tue, 31 Oct 2023 00:00:00 +0000

In a previous blog article, we showed how to configure the project description file to create a flexible project setup. We also showcased how this can be used to integrate common components - such as VUnit - into your project.

Moving Sigasi Files Out of the Way

Mon, 25 Sep 2023 00:00:00 +0000

Sigasi Visual HDL offers a range of powerful features that significantly enhance your coding experience. However, to unlock its full potential, it’s crucial to configure your projects properly. In this guide, we’ll present ways to create a streamlined project setup that keeps your Sigasi configuration files neatly organized and separated from your source code.

Use Case, Mixed Language VUnit Project

Mon, 25 Sep 2023 00:00:00 +0000

In the previous blog article, we showed how to configure the project description file to create flexible project setup. To illustrate the efficient use of linked resources in Sigasi Visual HDL (SVH), let’s walk through a scenario where we set up a project using only the project description file, while also utilizing virtual and linked resources for everything else, including library mapping and preferences.

One IP block per project

Sun, 22 Jan 2012 00:00:00 +0000

This article discusses how to manage reusable projects.

What is a reusable project?

If you have a set of HDL files, which are closely related and serve a single purpose, we will call this a reusable project. The files may include packages, modules, entities, and architectures. Often, these reusable projects take the form of an IP library (like the IEEE libraries) or an IP core (like a processor core or a memory controller). If you are working on large projects, such as a System on Chip (SoC) design, you are using IP cores.