Best-Practices on Sigasi

Enabling DO-254 guideline checks in Sigasi SVH

Mon, 09 Feb 2026 00:00:00 +0000

DO-254 (also known as ED-80, “Design Assurance Guidance for Airborne Electronic Hardware”) is the primary international guidance used for developing complex, safety-critical electronic hardware for civil aircraft. It was jointly developed by RTCA (US) and EUROCAE (EU). First published in 2000, DO-254 became widely adopted in the avionics industry after the FAA accepted it as a means of compliance for avionics design assurance.

Enabling STARC rules in Sigasi SVH

Tue, 27 Jan 2026 00:00:00 +0000

STARC — the Semiconductor Technology Academic Research Center — was a research consortium established by leading Japanese semiconductor companies. Back in 2006, it released the STARC RTL Design Style Guides, a comprehensive collection of rules, recommendations, and best practices for RTL design. The guides cover everything from design creation and code management to verification workflows and general project organization, with separate volumes for Verilog/SystemVerilog and VHDL.

Use Case: Minimal Project Setup

Tue, 31 Oct 2023 00:00:00 +0000

In a previous blog article, we showed how to configure the project description file to create a flexible project setup. We also showcased how this can be used to integrate common components - such as VUnit - into your project.

Moving Sigasi Files Out of the Way

Mon, 25 Sep 2023 00:00:00 +0000

Sigasi Visual HDL offers a range of powerful features that significantly enhance your coding experience. However, to unlock its full potential, it’s crucial to configure your projects properly. In this guide, we’ll present ways to create a streamlined project setup that keeps your Sigasi configuration files neatly organized and separated from your source code.

Use Case, Mixed Language VUnit Project

Mon, 25 Sep 2023 00:00:00 +0000

In the previous blog article, we showed how to configure the project description file to create flexible project setup. To illustrate the efficient use of linked resources in Sigasi Visual HDL (SVH), let’s walk through a scenario where we set up a project using only the project description file, while also utilizing virtual and linked resources for everything else, including library mapping and preferences.

One IP block per project

Sun, 22 Jan 2012 00:00:00 +0000

In earlier posts, We’ve explained that there are basically three ways to organize your VHDL code within your Sigasi environment:

No organization
One design in one folder
Aggregation of reusable projects (described in this article)

This article was updated in 2023. Sigasi Visual HDL (SVH) has evolved a lot since the original article from 2012. The way to organize reusable projects in 2012 is no longer supported. This article discusses how to manage reusable projects in recent versions of SVH.

One design in one folder

Thu, 29 Dec 2011 00:00:00 +0000

As discussed in How do you organize the source code of your hardware project?, you can organize your VHDL files in many ways in Sigasi. The three recommended ways are:

No organization
One design in one folder (described in this article)
One IP block per project

This article deals with the “one design – one folder” way of organizing a project. The basic idea is that all of the files for your new hardware design are in one folder on your hard drive. In addition to your own files, there might be some third party libraries that you need for your project, like the XilinxCoreLib or Altera_MF files.

No organization

Sat, 03 Dec 2011 00:00:00 +0000

The Sigasi development environment allows a very large flexibility on how to organize VHDL projects. So much in fact, that it can become confusing. Let me outline three recommended ways of organizing your VHDL project.