Case Statement on Sigasi

Case statements in VHDL and (System)Verilog

Thu, 17 Dec 2020 00:00:00 +0000

In programming languages, case (or switch) statements are used as a conditional statement in which a selection is made based on different values of a particular variable or expression. A general discussion of these statements can be found here .

Static Checks for VHDL Code

Wed, 03 Aug 2011 00:00:00 +0000

Sigasi Lint performs static analysis for VHDL code in order to find VHDL code lint . The built in VHDL linter will issue warning when you use certain suspicious VHDL constructions. While your code does not violate the VHDL syntax, there might be a problem with your code.