No VHDL Rename in Emacs VHDL mode

Wed, 15 Jun 2011 00:00:00 +0000

In my series of how Sigasi is better than Emacs VHDL mode, this entry deals with code reuse, more specifically with renaming.

Code Reuse

The situation where you write code once, produce a chip and never look at that code again is pretty rare. Usually, there is going to be a follow-up project. You might build an improved version of the chip, or you might want to reuse an old component for a completely new chip.

Code Reuse on Sigasi

No VHDL Rename in Emacs VHDL mode

Code Reuse