Editor on Sigasi

The benefits of early detection

Fri, 23 Sep 2022 00:00:00 +0000

This video is a recording of the webinar we organised on 13 and 15 September 2022 to teach about various productivity hacks when using Sigasi. Although Sigasi Studio has been depreciated, the content is also valid for Sigasi Visual HDL.

Graphical Editors: Yay or Nay

Mon, 31 Jan 2022 00:00:00 +0000

The Graphics Configuration feature has been deprecated since Sigasi Studio 4.16 and was removed in Sigasi Studio 5.3.

When creating hardware designs, graphical diagrams are a huge help in comprehending complex designs more easily. Diagrams are also convenient to share with others, for example as part of technical documentation.

Sigasi Studio Editing Tricks

Tue, 16 Nov 2021 00:00:00 +0000

10 Tricks to level up your editing skills

We all know the feeling when it’s pair programming time with a coworker: Suddenly we wonder in awe which keyboard shortcut they used a second ago to get the task done in no time. You bet there will be plenty of situations when your peer would be curious, too. The truth is, everyone has their own habits and favorite tools for code entry. Often it is only a subset of the editor’s functional range, though.

Checking case statements in SystemVerilog

Thu, 10 Dec 2020 00:00:00 +0000

Case statements are used a lot in SystemVerilog because they provide the most elegant way to describe state machines. In this video we show you how Sigasi Visual HDL helps you avoid typical mistakes.

Multi-dimensional array and record checks in VHDL

Thu, 10 Dec 2020 00:00:00 +0000

In the Sigasi Studio 4.10 release we have extended the vector size mismatch check to check vectors in records and multi-dimensional arrays.

Let’s look at a few examples.

The first example is a simple vector assignment. Sigasi flags the clear size mismatch: the declaration specifies 32 bits, the actual value of the VHDL2008 literal is only 30 bits. When we correct the size, the problem disappears immediately.

Snake Case subword navigation and selection

Thu, 17 Sep 2020 00:00:00 +0000

Sigasi Visual HDL has a lot of very useful keyboard shortcuts that make dealing with Verilog, VHDL and SystemVerilog a very smooth experience.

In Sigasi Studio 4.9 the Sigasi development team made a few tweaks to the “Next word” and “Previous word” shortcuts. It now has special support for Snake_case identifiers.

Auto-close brackets and quotes

Thu, 25 Jun 2020 00:00:00 +0000

Matching brackets are important when writing Verilog, VHDL and SystemVerilog. This video demonstrates how Sigasi Visual HDL helps you to balance your brackets by automatically closing them. We will also show you a trick to quickly navigate to a matching bracket.

Japanese, Korean and Chinese comments in HDL code

Wed, 25 Mar 2020 00:00:00 +0000

Editing Broken Code in Sigasi Studio

Thu, 12 Dec 2019 00:00:00 +0000

Prefix all signals in an instantiation

Fri, 11 Oct 2019 00:00:00 +0000

When you autocomplete an instantiation using the Sigasi Studio Content Assist, wire or signal names in the port map get a default value that is equal to the port name. In many designs, this can be insufficient. You might need to give the wires/signals in the portmap a prefix so they match the actual wire/signal names in the design.

Split Editor View

Thu, 19 Sep 2019 00:00:00 +0000

Want to see two HDL files side by side? Want to edit the bottom of a file and view the top of the file at the same time? This screencast shows how easy it is in Sigasi Visual HDL for Eclipse.

Smart Indentation for Verilog

Fri, 15 Jan 2016 00:00:00 +0000

You can find more info in the manual.

Smart Indent for VHDL

Fri, 01 Jan 2016 00:00:00 +0000

You can find more info in the manual.

Editors vs Emacs vs Sigasi matrix

Sun, 13 Jun 2010 00:00:00 +0000

	Editors	Emacs VHDL mode	Sigasi
Commercially supported	?	✘	✓
Syntax highlighting	✓	✓	✓
Semantic highlighting	✘	✘	✓

Word based autocomplete	✓	✓	✓
Language templates	?	✓	✓
Context sensitive template	✘	✘	✓
Instant error reporting	✘	✘	✓

Configurable key bindings	?	✓	✓
Extensible	?	✓ in LISP	✓
VHDL code formatting	✘	✓	✓

Navigation; search	✘	broken; based on CTAGS	✓
Rename refactoring	✘	✘	✓
Hover to see declaration	✘	✘	✓
Chip hierarchy	✘	limited	✓
Component instantiation	✘	✓ based on port translation	✓
Inspect values of constants and Generics	✘	✘	✓