Emacs on Sigasi

Why Emacs VHDL mode is so Great. And Why We Want to Beat it

Fri, 30 Mar 2012 00:00:00 +0000

Reto Zimmermann’s Emacs VHDL mode is one of the most advanced tools for VHDL entry on the planet. Other general purpose editors like VI and Notepad++ might be great editors, but they are also very “general purpose”. They have very few language specific features. The engineer is left with a tool that manipulates ASCII text, not with a tool that understands VHDL.

Better than Emacs VHDL mode

Mon, 28 Nov 2011 00:00:00 +0000

The big difference in approach between Sigasi and Emacs VHDL mode is this: Emacs uses regular expressions to make guesses about your code, while Sigasi has a real parser that understands your VHDL, Verilog, and SystemVerilog code. As a result you get:

Five reasons why Emacs will always be better

Fri, 02 Sep 2011 00:00:00 +0000

In the past months, we have made large efforts to make Emacs obsolete. After enquiring on some Emacs-friendly newsgroups, I can only conclude that we have indeed offered a better solution than Emacs, in most ways.

Room for Improvement

Fri, 24 Jun 2011 00:00:00 +0000

It is no secret that Sigasi wants to be better than Emacs VHDL mode. I have posted several articles about the fundamental differences between Emacs and Sigasi. It usually boils down to the limitations of regular expressions and pattern matching. There are just certain things that require a parser rather than a simple pattern matcher.

Code refactoring: Emacs VHDL mode vs Sigasi

Wed, 22 Jun 2011 00:00:00 +0000

Last week, I talked about that there is No VHDL Rename in Emacs VHDL mode. Rename is just the tip of the iceberg when it comes to code modifications or refactorings. There are dozens of well documented and automated code refactorings… in the world of software engineering. In hardware land, however, only a few refactoring tools exist. (You’re lucky: Sigasi is one of them!) And all the hardware refactoring tools put together still look pale compared to Eclipse JDT, the weapon of choice for many Java refactorers.

Sigasi Better than Emacs

Tue, 21 Jun 2011 00:00:00 +0000

Over the past few weeks, I have made an effort to demonstrate that Sigasi 2.0 is better than Emacs VHDL mode. I have also argued that Emacs VHDL mode used to be the best VHDL editor on the planet. In summary, I wrote about:

No VHDL Rename in Emacs VHDL mode

Wed, 15 Jun 2011 00:00:00 +0000

In my series of how Sigasi is better than Emacs VHDL mode, this entry deals with code reuse, more specifically with renaming.

Code Reuse

The situation where you write code once, produce a chip and never look at that code again is pretty rare. Usually, there is going to be a follow-up project. You might build an improved version of the chip, or you might want to reuse an old component for a completely new chip.

Engineers are smart enough to change editors

Tue, 07 Jun 2011 00:00:00 +0000

Too stupid or too stubborn?

A few weeks ago, one of my colleagues at Sigasi (a VI user himself) stated that anybody who is not using Emacs for their VHDL work will either be too stubborn or too stupid to switch to Sigasi. (Note: this was a personal opinion and not the official company position). He had been using VI (gvim actually) for all of his VHDL work years ago. As he learned more out about the great features of the Emacs VHDL mode, he concluded that he himself had probably been too stubborn to switch. Other text editors (VI, Notepad++, UltraEdit, Crimson) may be highly configurable and versatile, but they are not highly adapted to VHDL (or to any other language, for that matter).

Emacs Syntax errors

Wed, 01 Jun 2011 00:00:00 +0000

Here is a new example of why Sigasi is better than Emacs VHDL mode: syntax checking.

In Emacs VHDL mode, there is no built-in syntax checker. This design decision was perfectly reasonable in the early 1990s, when the Emacs VHDL mode was created. Because of the processing power and the memory available at that time, compilation was a slow process that was best handled by specialized tools. So Emacs uses a simulator (like ModelSim) to check the syntax of VHDL code.

Emacs Code Coloring is Outdated

Wed, 18 May 2011 00:00:00 +0000

In my series of how Sigasi is better than Emacs VHDL mode, I want to talk about code coloring.

Syntax Highlighting

Code coloring consists of two parts: syntax highlighting and semantic highlighting. Most any editor does the former. The keywords are colored, strings, numbers and comments all highlighted in a separate color. All of this is possible using simple regular expressions (regex).

VHDL Emacs mode navigation using ctags are broken

Fri, 13 May 2011 00:00:00 +0000

In my series of how Sigasi is better than Emacs VHDL mode , we want to demonstrate that Emacs VHDL mode is becoming outdated. I do this by comparing relevant and technical features of the Emacs VHDL mode and Sigasi.

HDL Editors vs. HDL Editors

Mon, 20 Dec 2010 00:00:00 +0000

A (relatively) painless upgrade path for VI and Emacs users

One editor is not as good as the next. Likewise, one HDL editor is not as good as the next. In fact, even the word HDL editor is not chosen correctly. You want to design your hardware, you don’t want to edit HDL. VHDL or Verilog is just a means to an end.

Editors vs Emacs vs Sigasi matrix

Sun, 13 Jun 2010 00:00:00 +0000

	Editors	Emacs VHDL mode	Sigasi
Commercially supported	?	✘	✓
Syntax highlighting	✓	✓	✓
Semantic highlighting	✘	✘	✓

Word based autocomplete	✓	✓	✓
Language templates	?	✓	✓
Context sensitive template	✘	✘	✓
Instant error reporting	✘	✘	✓

Configurable key bindings	?	✓	✓
Extensible	?	✓ in LISP	✓
VHDL code formatting	✘	✓	✓

Navigation; search	✘	broken; based on CTAGS	✓
Rename refactoring	✘	✘	✓
Hover to see declaration	✘	✘	✓
Chip hierarchy	✘	limited	✓
Component instantiation	✘	✓ based on port translation	✓
Inspect values of constants and Generics	✘	✘	✓