<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Empty Range on Sigasi</title><link>https://www.sigasi.com/tags/empty-range/</link><description>Recent content in Empty Range on Sigasi</description><generator>Hugo</generator><language>en</language><lastBuildDate>Wed, 03 Aug 2011 00:00:00 +0000</lastBuildDate><atom:link href="https://www.sigasi.com/tags/empty-range/index.xml" rel="self" type="application/rss+xml"/><item><title>Static Checks for VHDL Code</title><link>https://www.sigasi.com/legacy/tech/static-checks-vhdl-code/</link><pubDate>Wed, 03 Aug 2011 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/legacy/tech/static-checks-vhdl-code/</guid><description>&lt;p&gt;&lt;a
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 &gt;Sigasi Lint&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt; performs static analysis for VHDL code in order to find VHDL code &lt;a
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 href="https://en.wikipedia.org/wiki/Lint_%28software%29"
 
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 &gt;lint&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt;. The built in VHDL linter will issue warning when you use certain suspicious VHDL constructions. While your code does not violate the VHDL syntax, there might be a problem with your code.&lt;/p&gt;</description></item></channel></rss>