<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>JanHDL on Sigasi</title><link>https://www.sigasi.com/tags/janhdl/</link><description>Recent content in JanHDL on Sigasi</description><generator>Hugo</generator><language>en</language><lastBuildDate>Mon, 19 Sep 2011 00:00:00 +0000</lastBuildDate><atom:link href="https://www.sigasi.com/tags/janhdl/index.xml" rel="self" type="application/rss+xml"/><item><title>Fixing Verilog is easy</title><link>https://www.sigasi.com/opinion/jan/fixing-verilog-easy/</link><pubDate>Mon, 19 Sep 2011 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/fixing-verilog-easy/</guid><description>&lt;p&gt;The example in my previous post &amp;ldquo;Wasting real time in zero time&amp;rdquo; has triggered some interesting responses, providing more than enough material for a follow-up post. VHDL designers beware, hardcore Verilog stuff ahead!&lt;/p&gt;</description></item><item><title>Pitfalls for circuit girls</title><link>https://www.sigasi.com/opinion/jan/pitfalls-for-circuit-girls/</link><pubDate>Thu, 10 Feb 2011 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/pitfalls-for-circuit-girls/</guid><description>&lt;h2 
 class="uk-heading-large" 
 id="the-circuit-girl"&gt;
 &lt;a
 href="https://www.sigasi.com/opinion/jan/pitfalls-for-circuit-girls/#the-circuit-girl"
 class="uk-link-reset"
 aria-label="Link to this section: The Circuit Girl"&gt;
 The Circuit Girl
 &lt;/a&gt;
&lt;/h2&gt;
&lt;p&gt;Some time ago I heard about a video with FPGA design book recommendations by &lt;a
 style="white-space: nowrap;"
 href="https://en.wikipedia.org/wiki/Jeri_Ellsworth"
 
 target="_blank"
 
 &gt;Jeri Ellsworth&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt;, who is also known as the &lt;em&gt;Circuit Girl&lt;/em&gt;. I admit that the concept of &lt;a
 style="white-space: nowrap;"
 href="https://www.urbandictionary.com/define.php?term=circuit%20girl"
 
 target="_blank"
 
 &gt;circuit girls&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt; triggered my imagination. Somehow I feel like there should be more of those. Consequently, I checked out &lt;a
 style="white-space: nowrap;"
 href="https://www.youtube.com/watch?v=kobf8IOB0oA"
 
 target="_blank"
 
 &gt;her video&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt; without further delay.&lt;/p&gt;</description></item><item><title>Time for reflection</title><link>https://www.sigasi.com/opinion/jan/time-reflection/</link><pubDate>Fri, 17 Dec 2010 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/time-reflection/</guid><description>&lt;p&gt;Dear reader,&lt;/p&gt;
&lt;p&gt;In my previous post, &lt;a
 style="white-space: nowrap;"
 href="https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/"
 
 &gt;VHDL&amp;rsquo;s crown jewel&lt;/a&gt;, I announced further considerations about nondeterminism in Verilog. However, I am getting worried that you may be losing interest. As a visitor of the Sigasi site, you are likely a VHDL design professional, or aspiring to become one. Why should you care about Verilog? Moreover, you are probably a busy person, looking for productivity solutions in your day-to-day work. What is the relevancy of all this pseudo-philosophical talk about nondeterminism? Before continuing, I think I have to give you an indication of where I am heading.&lt;/p&gt;</description></item><item><title>VHDL's crown jewel</title><link>https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/</link><pubDate>Wed, 03 Nov 2010 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/</guid><description>&lt;h2 
 class="uk-heading-large" 
 id="how-vhdl-preserves-determinism"&gt;
 &lt;a
 href="https://www.sigasi.com/opinion/jan/vhdls-crown-jewel/#how-vhdl-preserves-determinism"
 class="uk-link-reset"
 aria-label="Link to this section: How VHDL preserves determinism"&gt;
 How VHDL preserves determinism
 &lt;/a&gt;
&lt;/h2&gt;
&lt;p&gt;In this post, I would like to talk about VHDL&amp;rsquo;s crown jewel: how it preserves determinism in a concurrent language. Here is a figure of how it works:&lt;/p&gt;</description></item><item><title>Your favorite mistake</title><link>https://www.sigasi.com/opinion/jan/your-favorite-mistake/</link><pubDate>Wed, 08 Sep 2010 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/your-favorite-mistake/</guid><description>&lt;p&gt;As a visitor of the Sigasi website, you are probably interested in Sigasi&amp;rsquo;s products. Therefore, there is a good chance that you are using VHDL and that you like it. (If you are here for other reasons or if you hate VHDL, you are most welcome too :-))&lt;/p&gt;</description></item><item><title>EDA 2.0</title><link>https://www.sigasi.com/opinion/jan/eda-20/</link><pubDate>Sun, 30 May 2010 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/jan/eda-20/</guid><description>&lt;p&gt;It has been quiet around this corner for some time, but on the broader Sigasi front, a lot has happened. Previously it was only available as a standalone product, which somewhat hided its Eclipse foundation.&lt;/p&gt;</description></item></channel></rss>