Mythbuster on Sigasi

VHDL Physical Type is not Synthesizable, or is it? (part 2)

Mon, 15 Oct 2012 00:00:00 +0000

In a previous post, VHDL Physical Type is not Synthesizable, or is it?, I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that the synthesis tool does not really have to deal with physical types at all.

VHDL Physical Type is not Synthesizable, or is it?

Thu, 11 Oct 2012 00:00:00 +0000

Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following “wisdom”:

Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]

VHDL case statements can do without the "others"

Mon, 24 Oct 2011 00:00:00 +0000

I was talking to some engineering students the other day, as they were doing a VHDL lab. I noticed a VHDL case statement for state machine with named states (enumerated data type). All states were handled in their VHDL case statement, and still they put an others section in their code. I had a hard time explaining that this clause was useless. The students mumbled something about their professor eating them alive if they’d forget the others and problems with uninitialized stated and high-impedance state. As you might know, these concepts are related to the std_ulogic and std_logic type, but not to enumerated types.