https://www.sigasi.com/tags/osvvm/Recent content in OSVVM on SigasiHugoenWed, 24 May 2023 00:00:00 +0000https://www.sigasi.com/knowledge/how_tos/osvvm-project/Wed, 24 May 2023 00:00:00 +0000https://www.sigasi.com/knowledge/how_tos/osvvm-project/<p><a style="white-space: nowrap;" href="https://osvvm.org/" target="_blank" ><strong>open-source VHDL Verification Methodology (OSVVM)</strong>&nbsp;<span uk-icon="icon: sign-out; ratio: 0.7"></span></a> is an advanced <strong>verification methodology</strong> for <strong>digital hardware design</strong>. As the name suggest, it is based on <a style="white-space: nowrap;" href="https://en.wikipedia.org/wiki/VHDL" target="_blank" >VHDL&nbsp;<span uk-icon="icon: sign-out; ratio: 0.7"></span></a>. OSVVM can be seen as the VHDL counterpart of <a style="white-space: nowrap;" href="https://en.wikipedia.org/wiki/Universal_Verification_Methodology" target="_blank" >UVM&nbsp;<span uk-icon="icon: sign-out; ratio: 0.7"></span></a>.</p>