<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>PoC on Sigasi</title><link>https://www.sigasi.com/tags/poc/</link><description>Recent content in PoC on Sigasi</description><generator>Hugo</generator><language>en</language><lastBuildDate>Tue, 14 Jun 2016 00:00:00 +0000</lastBuildDate><atom:link href="https://www.sigasi.com/tags/poc/index.xml" rel="self" type="application/rss+xml"/><item><title>PoC - A Pile of Cores</title><link>https://www.sigasi.com/opinion/poc-a-pile-of-cores/</link><pubDate>Tue, 14 Jun 2016 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/opinion/poc-a-pile-of-cores/</guid><description>&lt;h2 
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&lt;p&gt;This article introduces our IP core library called &lt;a
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 href="https://github.com/VLSI-EDA/PoC"
 
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 &gt;&lt;strong&gt;PoC&lt;/strong&gt;&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt;, a free and open-source library of vendor-independent IP
cores, maintained by the &lt;a
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 &gt;&lt;strong&gt;Chair for VLSI Design, Diagnostics and Architecture&lt;/strong&gt;&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt; of &lt;strong&gt;Prof. Spallek&lt;/strong&gt;, at the &lt;a
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 &gt;&lt;strong&gt;Technische Universität Dresden&lt;/strong&gt;&amp;nbsp;&lt;span uk-icon="icon: sign-out; ratio: 0.7"&gt;&lt;/span&gt;&lt;/a&gt;, &lt;strong&gt;Germany&lt;/strong&gt;. We present the development of our IP core library, the accompanying Python-based infrastructure and how
we improved PoC&amp;rsquo;s VHDL source files with the help of Sigasi Studio.&lt;/p&gt;</description></item></channel></rss>