<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Preprocessor on Sigasi</title><link>https://www.sigasi.com/tags/preprocessor/</link><description>Recent content in Preprocessor on Sigasi</description><generator>Hugo</generator><language>en</language><lastBuildDate>Tue, 02 Aug 2022 00:00:00 +0000</lastBuildDate><atom:link href="https://www.sigasi.com/tags/preprocessor/index.xml" rel="self" type="application/rss+xml"/><item><title>VHDL 2019: Conditional Analysis</title><link>https://www.sigasi.com/tech/vhdl-conditional-analysis/</link><pubDate>Tue, 02 Aug 2022 00:00:00 +0000</pubDate><guid>https://www.sigasi.com/tech/vhdl-conditional-analysis/</guid><description>&lt;p&gt;If you are writing universal, portable VHDL code, be it a design that targets multiple chip families, or a library that should work with multiple simulators, you may have noticed that it can be quite challenging to make things work everywhere.
Different vendors provide their own macros and IPs, simulators provide their own utility libraries, tools support different VHDL attributes. Your code may be treated differently or even fail to compile if it uses language features that are not supported by one of the tools.&lt;/p&gt;</description></item></channel></rss>