Preprocessor on Sigasi

VHDL 2019: Conditional Analysis

Tue, 02 Aug 2022 00:00:00 +0000

If you are writing universal, portable VHDL code, be it a design that targets multiple chip families, or a library that should work with multiple simulators, you may have noticed that it can be quite challenging to make things work everywhere. Different vendors provide their own macros and IPs, simulators provide their own utility libraries, tools support different VHDL attributes. Your code may be treated differently or even fail to compile if it uses language features that are not supported by one of the tools.

Cross project includes in SystemVerilog

Tue, 06 Oct 2020 00:00:00 +0000

In this article, we discuss how in Sigasi Studio one can include a SystemVerilog file from a different project. Splitting up large designs in different projects, e.g. one project per IP block and one project for the top level, makes these projects easier to manage and fosters IP reuse.

Preprocessor macro expansion

Thu, 25 Jun 2020 00:00:00 +0000

Working with preprocessors can be frustrating. Includes and macro expansions are very powerful; but if you make any typo, figuring out what went wrong can be really painful.

In this video you will learn how Sigasi can help you write and understand preprocessor code like macro’s and defines with flair.

Configure include paths in Sigasi Visual HDL for Eclipse

Thu, 21 Mar 2019 00:00:00 +0000

Autocompletes for Verilog and SystemVerilog defines and includes

Wed, 20 Jun 2018 00:00:00 +0000

The Preprocessor View is documented here.