Project Management on Sigasi

Use Case: Minimal Project Setup

Tue, 31 Oct 2023 00:00:00 +0000

In a previous blog article, we showed how to configure the project description file to create a flexible project setup. We also showcased how this can be used to integrate common components - such as VUnit - into your project.

Moving Sigasi Files Out of the Way

Mon, 25 Sep 2023 00:00:00 +0000

Sigasi Visual HDL offers a range of powerful features that significantly enhance your coding experience. However, to unlock its full potential, it’s crucial to configure your projects properly. In this guide, we’ll present ways to create a streamlined project setup that keeps your Sigasi configuration files neatly organized and separated from your source code.

Use Case, Mixed Language VUnit Project

Mon, 25 Sep 2023 00:00:00 +0000

In the previous blog article, we showed how to configure the project description file to create flexible project setup. To illustrate the efficient use of linked resources in Sigasi Visual HDL (SVH), let’s walk through a scenario where we set up a project using only the project description file, while also utilizing virtual and linked resources for everything else, including library mapping and preferences.

Build systems for HDL projects

Tue, 04 May 2021 00:00:00 +0000

Introduction

For a long time, software developers have enjoyed build systems to help them build their code. These build systems keep track of dependencies and call the appropriate tools to run the design flow or parts thereof. In this article, we try to give an overview of currently available build tools for VHDL and (System)Verilog projects.

Import a project in Sigasi Visual HDL from `.f` files

Tue, 23 Feb 2021 00:00:00 +0000

Dot-f (.f) files are a ‘de facto’ standard for exchanging project information between EDA tools and managing HDL files in bigger FPGA and ASIC projects. In this article we discuss the .f file format, its limitations, and how to use it to create a Sigasi Visual HDL (SVH) project from your HDL code and .f file(s).

Scripting Sigasi project creation

Thu, 17 Oct 2013 00:00:00 +0000

When you start using Sigasi, the first thing you have to do is Setting Up a Project. This consists of two steps: (1) selecting the VHDL files that you want in your project and (2) configuring in which VHDL library these files must be mapped. In most cases you already have this information in one form or another. For example in a makefile, in a Tcl simulation script, or in the project descriptor file of a third-party EDA tool.