Python on Sigasi

Import a project in Sigasi Visual HDL from `.f` files

Tue, 23 Feb 2021 00:00:00 +0000

Dot-f (.f) files are a ‘de facto’ standard for exchanging project information between EDA tools and managing HDL files in bigger FPGA and ASIC projects. In this article, we discuss the .f file format, its limitations, and how to use it to create a Sigasi Visual HDL (SVH) project from your HDL code and .f file(s).

Importing a Quartus project in Sigasi Visual HDL

Fri, 30 Mar 2018 00:00:00 +0000

For some time it has been possible to integrate Sigasi Visual HDL (SVH) in Altera Quartus. Through feedback from our users, we have seen that this approach is good when starting a project or taking off with SVH on an existing Altera Quartus project. However, as a project grows and when more of the development work happens in SVH, keeping the link to the Altera Quartus project often gets in the way. Switching to a separate SVH project is more flexible. For example, this allows to show the source files in a hierarchical way in the Project Explorer.