Recovering Parser on Sigasi

Recovering Verilog and SystemVerilog Parser

Fri, 31 Jan 2020 00:00:00 +0000

When you’re writing HDL code, be it in SystemVerilog, Verilog or VHDL, your code is broken or incomplete most of the time. Any regular compiler stops on the first error it encounters and will often only show an obscure error message. At Sigasi, we are convinced productivity and happiness of HDL developers increase when they receive immediate feedback on broken code.

One mistake, one error marker

Fri, 21 Sep 2012 00:00:00 +0000

Ideally, if you make one mistake in VHDL, you want your compiler to show one error marker. Here is a small example.

For this single mistake, Sigasi flags one error marker:

Recovering VHDL Parser

Fri, 21 Sep 2012 00:00:00 +0000

It is useful to analyze code that is only partly finished, code that still has errors in it. Analyzing broken code helps people understand, improve and complete the code. In order to perform such an analysis, you need a parser that recovers after it encounters an error. In the world of hardware design, hardly any recovering parsers exist and engineers are left out in the cold. All but a few EDA tools fail miserably at parsing incorrect VHDL code.

Three mistakes, three error markers

Fri, 21 Sep 2012 00:00:00 +0000

Ideally, if you make three mistakes in VHDL, you want to see three error markers. Here is a small example.

A traditional VHDL compiler gives only one error message. You will have to fix this error and start the compiler again before you can find the next error. This takes extra time and you need all of your time you to work on complex design problems that you are dealing with.