RTL on Sigasi

Write Better HDL, Before It Breaks Your Design

Wed, 15 Oct 2025 00:00:00 +0000

Discover how real-time linting in Sigasi Visual HDL helps you catch issues earlier, improve code quality, and accelerate your development flow.

How to code resets in Verilog

Mon, 04 May 2026 00:00:00 +0000

In digital design, resets are used to bring a circuit into a predefined state after power-up. This article focuses on how to design resets for synchronous digital circuits in Verilog and SystemVerilog.

12,000 Downloads and Counting

Thu, 11 Dec 2025 00:00:00 +0000

It took us more than one year to get to 10,000 downloads. In less than 2 months, 2,000 more downloads were done. Our mission to empower design and verification engineers to save time and costs for their team/company pays off.

10,000 Downloads and Counting

Mon, 29 Sep 2025 00:00:00 +0000

One year ago, we introduced Sigasi® Visual HDL™ on the VS Code Marketplace. Our goal was clear: empower design and verification engineers to write faster, higher-quality RTL code and save time and costs for their team/company.

Introducing Linting In Chip Design Flow

Tue, 16 Sep 2025 00:00:00 +0000

In complex ASIC and FPGA designs, quality cannot be postponed to simulation. Issues introduced during RTL design cause bloating verification cycles, consuming costly engineering time, and risking expensive silicon re-spins.

VHDL Physical Type is not Synthesizable, or is it? (part 2)

Mon, 15 Oct 2012 00:00:00 +0000

In a previous post, VHDL Physical Type is not Synthesizable, or is it?, I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that the synthesis tool does not really have to deal with physical types at all.

VHDL Physical Type is not Synthesizable, or is it?

Thu, 11 Oct 2012 00:00:00 +0000

Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following “wisdom”:

Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]

Clock edge detection

Mon, 09 Apr 2012 00:00:00 +0000

There are two largely accepted ways to detect clock edges, and many style books prescribe or prefer one over the other. Let’s investigate.

This article deals with edge detection in synthesizable code, not with behavioral code as found in testbenches and behavioral models.

VHDL Pragmas

Tue, 05 Apr 2011 00:00:00 +0000

In VHDL, some tools support so-called compiler directives. A compiler directive, or pragma is additional information that you give to the VHDL compiler (the simulator or synthesis tool). While your directive has no influence on the VHDL code itself, it changes the behavior. The IEEE, in their VHDL RTL standard, defines a pragma as A generic term used to deﬁne a construct with no predeﬁned language semantics that inﬂuences how a synthesis tool will synthesize VHDL code into an equivalent hardware representation.