State Machine on Sigasi

Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others

Fri, 06 Mar 2020 00:00:00 +0000

State diagram in Sigasi Visual HDL Professional

In VHDL, Finite State Machines (FSMs) can be written in various ways. This article addresses the encoding of, and the data types used, for the state register. The encoding of the states of an FSM affects its performance in terms of speed, resource usage (registers, logic) and potentially power consumption. As we will see, enumerated datatypes are preferred for clarity and easy of maintenance.

Graphical representation of SystemVerilog State Machines

Wed, 20 Jun 2018 00:00:00 +0000

The State Machine View is documented here.

The Graphics Configuration File

Wed, 06 Dec 2017 00:00:00 +0000

Using Sigasi Studio's Graphics Configuration

Thu, 31 Aug 2017 00:00:00 +0000

The Graphics Configuration feature has been deprecated since Sigasi Studio 4.16 and was removed in Sigasi Studio 5.3.

The BlockDiagram- and StateMachine views are a very useful way to explore and understand HDL designs. But sometimes it just doesn’t cut it. The diagrams are too complex and crowded to understand a design. For this reason, the diagrams also can not always be easily directly used in documentation. Today we present a solution for this challenge.

Improve State Machine Conditional Analysis

Mon, 01 Jan 0001 00:00:00 +0000

Use static code analysis to find all conditions on state machine transitions. Reduce the resulting conditions to a simplified form, and correctly label the branches in our state machine diagrams.