Static Analysis on Sigasi

AI in Chip Design - Scaffolding with Sigasi

Wed, 28 Jan 2026 00:00:00 +0000

Join us on March 24th for our AI in Chip Design webinar and learn how you turn AI from a chaos multiplier into a throughput multiplier with a practical playbook: “AI allowed, but only through the wall”

Linting with Sigasi (on demand)

Wed, 15 Oct 2025 00:00:00 +0000

Missed our Linting with Sigasi Visual HDL webinar?

No worries, you can now watch the recorded webinar on demand. Fill in the form and you will receive the webinar and the very interesting Q&A’s.

AI is Probabilistic. Sign-off is deterministic.

Wed, 25 Feb 2026 00:00:00 +0000

How to integrate AI safely into RTL development — without compromising engineering discipline.

Sigasi, your first line of defense

Wed, 28 Jan 2026 00:00:00 +0000

A recent GPTZero investigation should make every engineer pause. They scanned 4,841 accepted NeurIPS 2025 papers and reported 100+ confirmed hallucinated citations spread across 50+ papers; issues that slipped past “3+ reviewers” per paper.

AI in Chip Design - Webinar

Mon, 26 Jan 2026 00:00:00 +0000

Join us on March 24th for our first webinar on AI. You’ll learn how Sigasi’s approach allows you to safely integrate AI in Chip Design. A must watch for engineers that want to go faster by using AI but don’t want to take the risks associated with AI.

12,000 Downloads and Counting

Thu, 11 Dec 2025 00:00:00 +0000

It took us more than one year to get to 10,000 downloads. In less than 2 months, 2,000 more downloads were done. Our mission to empower design and verification engineers to save time and costs for their team/company pays off.

10,000 Downloads and Counting

Mon, 29 Sep 2025 00:00:00 +0000

One year ago, we introduced Sigasi® Visual HDL™ on the VS Code Marketplace. Our goal was clear: empower design and verification engineers to write faster, higher-quality RTL code and save time and costs for their team/company.

Introducing Linting In Chip Design Flow

Tue, 16 Sep 2025 00:00:00 +0000

In complex ASIC and FPGA designs, quality cannot be postponed to simulation. Issues introduced during RTL design cause bloating verification cycles, consuming costly engineering time, and risking expensive silicon re-spins.

Improve State Machine Conditional Analysis

Mon, 01 Jan 0001 00:00:00 +0000

Use static code analysis to find all conditions on state machine transitions. Reduce the resulting conditions to a simplified form, and correctly label the branches in our state machine diagrams.