Syntax on Sigasi

Signal Assignments in VHDL: with/select, when/else and case

Thu, 05 Jun 2025 00:00:00 +0000

VHDL provides several ways to assign values to a signal based on the value of another. Most of the time, there’s more than one valid approach, and each has its advantages depending on clarity, maintainability, and tool support. This guide covers three primary idioms: selected signal assignment (with/select), conditional signal assignment (when/else), and case statements inside processes.
VHDL-2008 introduced a 4th idiom: pattern matching in case statements. We’ll conclude with practical considerations for using the right construct.

ANSI and Non-ANSI Port Declarations in Verilog

Wed, 02 Aug 2023 00:00:00 +0000

In Verilog, module ports can be declared using one of two styles: ANSI or non-ANSI. This article covers the distinct syntaxes of these two styles, as well as further differences between them.

Records in VHDL: Initialization and Constraining unconstrained fields

Tue, 31 Mar 2020 00:00:00 +0000

In VHDL, records help the designer organize data that belongs together. By using records, VHDL code will be easier to understand and maintain. This article highlights a couple of slightly more advanced aspects of record types in VHDL, namely how to use record constants, and how to use unconstrained data types as fields in records. We’ll see that, apart from some particular syntax, records are fairly easy to use after all.

Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others

Fri, 06 Mar 2020 00:00:00 +0000

State diagram in Sigasi Visual HDL Professional

In VHDL, Finite State Machines (FSMs) can be written in various ways. This article addresses the encoding of, and the data types used, for the state register. The encoding of the states of an FSM affects its performance in terms of speed, resource usage (registers, logic) and potentially power consumption. As we will see, enumerated datatypes are preferred for clarity and easy of maintenance.

"Use" and "Library" in VHDL

Mon, 09 Sep 2013 00:00:00 +0000

Beginning VHDL engineers, and advanced engineers too, can get confused about the exact scope of a use clause and a library clause in VHDL. They usually show up at the top of a file, which would make you think that they are visible in the entire file. Unfortunately, the truth is a bit more complex.

VHDL Pragmas

Tue, 05 Apr 2011 00:00:00 +0000

In VHDL, some tools support so-called compiler directives. A compiler directive, or pragma is additional information that you give to the VHDL compiler (the simulator or synthesis tool). While your directive has no influence on the VHDL code itself, it changes the behavior. The IEEE, in their VHDL RTL standard, defines a pragma as A generic term used to deﬁne a construct with no predeﬁned language semantics that inﬂuences how a synthesis tool will synthesize VHDL code into an equivalent hardware representation.