Synthesis on Sigasi

VHDL Physical Type is not Synthesizable, or is it? (part 2)

Mon, 15 Oct 2012 00:00:00 +0000

In a previous post, VHDL Physical Type is not Synthesizable, or is it?, I pointed out that VHDL synthesis tools can indeed synthesize VHDL physical types. In the example I gave, all computations with physical types were done at elaboration time, so that the synthesis tool does not really have to deal with physical types at all.

VHDL Physical Type is not Synthesizable, or is it?

Thu, 11 Oct 2012 00:00:00 +0000

Everybody who has been taught VHDL in college or in a company with senior colleagues has heard the following “wisdom”:

Pysical types are for simulation only. They cannot be synthesized. [commonly heard claim – debunked in this article]

Clock edge detection

Mon, 09 Apr 2012 00:00:00 +0000

There are two largely accepted ways to detect clock edges, and many style books prescribe or prefer one over the other. Let’s investigate.

This article deals with edge detection in synthesizable code, not with behavioral code as found in testbenches and behavioral models.

VHDL Pragmas

Tue, 05 Apr 2011 00:00:00 +0000

In VHDL, some tools support so-called compiler directives. A compiler directive, or pragma is additional information that you give to the VHDL compiler (the simulator or synthesis tool). While your directive has no influence on the VHDL code itself, it changes the behavior. The IEEE, in their VHDL RTL standard, defines a pragma as A generic term used to deﬁne a construct with no predeﬁned language semantics that inﬂuences how a synthesis tool will synthesize VHDL code into an equivalent hardware representation.