SystemVerilog on Sigasi

Webinar Survey

Tue, 13 Jan 2026 00:00:00 +0000

Thank you for joining us on our first webinar on October 15th, 2025.

As we haven’t seen you at the Visualization & Navigation Webinar on November 27th and you did not yet register for the Verification Frameworks on January 28th, we would like to get your feedback. Thank you for answering the following questions and helping us improve the webinars.

Keep verification focused on real bugs

Thu, 29 Jan 2026 00:00:00 +0000

Verification capacity isn’t scaling with design complexity. In the latest Wilson Research trend reports referenced here, 87% of FPGA projects reported non-trivial bug escapes, and IC/ASIC first-silicon success was only 14%.

Reduce avoidable RTL churn

Thu, 29 Jan 2026 00:00:00 +0000

Sigasi turns VS Code into a professional HDL engineering workspace for VHDL, SystemVerilog, and mixed-language projects. It provides deterministic, project-aware feedback while engineers write RTL, so teams spend less time on avoidable rework and more time on real design progress.

Done doesn't mean "correct"

Mon, 19 Jan 2026 00:00:00 +0000

If you’re managing chip projects, the hardest part isn’t writing/generating more RTL; it’s predicting verification + debug. This isn’t an “FPGA problem” or an “ASIC problem.” It’s a verification predictability problem.

Verification is eating the schedule

Fri, 12 Dec 2025 00:00:00 +0000

The 2024 Wilson Research Group Functional Verification Trend Reports point to a harsh reality: design complexity is rising faster than verification capacity, and the industry is paying for it in escapes, respins, and delays.

Verification Frameworks - Webinar on demand

Tue, 02 Dec 2025 00:00:00 +0000

On January 28th we presented our first webinar in 2026, in which we showed how Sigasi’s shift-left approach saves you valuable time and money in verification. A must watch for design & verification engineers in both SystemVerilog and VHDL.

Verilog Assignments: blocking or non-blocking?

Mon, 27 Oct 2025 00:00:00 +0000

Verilog / SystemVerilog has two different assignment operators. One assignment operator is blocking, the other one non-blocking. In this article, we’ll discuss how they are different and when to use each of them. Note that we’re talking about assignments in procedures (always, initial etc.) only, and not about continuous assignments.

ANSI and Non-ANSI Port Declarations in Verilog

Wed, 02 Aug 2023 00:00:00 +0000

In Verilog, module ports can be declared using one of two styles: ANSI or non-ANSI. This article covers the distinct syntaxes of these two styles, as well as further differences between them.

Sigasi's Software Development Kit Part 2

Mon, 30 May 2022 00:00:00 +0000

In the previous installment of this blog, we talked about why you would want to integrate Sigasi’s SDK into your own product portfolio. To summarize our arguments:

The SDK allows you to offer an editing experience in your own product line that is similar to a full blown IDE.
Developing such capabilities from scratch would be prohibitively expensive.

So, hopefully by now you’re convinced you want to license our SDK … but now what? In this installment, we want to focus on some practical aspects of integrating our SDK. The goal is to make you aware of the (limited) additional work you might be confronted with.

Sigasi's Software Development Kit Part 1

Mon, 25 Apr 2022 00:00:00 +0000

At Sigasi, we build tools to make you more productive. Specifically, we enhance your productivity during chip design with SystemVerilog and/or VHDL. For this purpose, two product lines are provided: Sigasi Studio for Eclipse and our Sigasi for VS Code extension. Both are focused on end-users.

Choose your Verilog formatter

Thu, 17 Mar 2022 00:00:00 +0000

When it comes to sharing your project code in a team, consistent formatting is important. This makes your code more readable for your colleagues or customers. The Sigasi Studio 4.15 release offers an additional choice to format Verilog and SystemVerilog code. You now can opt to use Verible for formatting your code in Sigasi Visual HDL.

Case statements in VHDL and (System)Verilog

Thu, 17 Dec 2020 00:00:00 +0000

In programming languages, case (or switch) statements are used as a conditional statement in which a selection is made based on different values of a particular variable or expression. A general discussion of these statements can be found here .

Checking case statements in SystemVerilog

Thu, 10 Dec 2020 00:00:00 +0000

Case statements are used a lot in SystemVerilog because they provide the most elegant way to describe state machines. In this video we show you how Sigasi Visual HDL helps you avoid typical mistakes.

Actual? Formal? What do they mean?

Wed, 14 Oct 2020 00:00:00 +0000

In this article, we discuss the terms actual and formal. These terms show up in the Language Reference Manual of VHDL and (System)Verilog, and they also show up in some of the error messages in Sigasi Visual HDL. Actuals and formals are short for actual and formal arguments of functions, procedures, entities, modules…

Cross project includes in SystemVerilog

Tue, 06 Oct 2020 00:00:00 +0000

In this article, we discuss how in Sigasi Studio one can include a SystemVerilog file from a different project. Splitting up large designs in different projects, e.g. one project per IP block and one project for the top level, makes these projects easier to manage and fosters IP reuse.

Wildcards in sensitivity lists in VHDL and Verilog

Mon, 28 Sep 2020 00:00:00 +0000

In hardware description languages (HDL), sensitivity lists are used to indicate which events may trigger a VHDL process or (System)Verilog always statement. These trigger events are usually transitions of signals that are inputs of the process or always statement.

Checking module instantiations

Thu, 17 Sep 2020 00:00:00 +0000

All Verilog and SystemVerilog projects use modules and module instantiations. In this video, we’ll show you how Sigasi Visual HDL helps you get these instantiations right, even when the code changes.

Preprocessor macro expansion

Thu, 25 Jun 2020 00:00:00 +0000

Working with preprocessors can be frustrating. Includes and macro expansions are very powerful; but if you make any typo, figuring out what went wrong can be really painful.

In this video you will learn how Sigasi can help you write and understand preprocessor code like macro’s and defines with flair.

Recovering Verilog and SystemVerilog Parser

Fri, 31 Jan 2020 00:00:00 +0000

When you’re writing HDL code, be it in SystemVerilog, Verilog or VHDL, your code is broken or incomplete most of the time. Any regular compiler stops on the first error it encounters and will often only show an obscure error message. At Sigasi, we are convinced productivity and happiness of HDL developers increase when they receive immediate feedback on broken code.

Prefix all signals in an instantiation

Fri, 11 Oct 2019 00:00:00 +0000

When you autocomplete an instantiation using the Sigasi Studio Content Assist, wire or signal names in the port map get a default value that is equal to the port name. In many designs, this can be insufficient. You might need to give the wires/signals in the portmap a prefix so they match the actual wire/signal names in the design.

SystemVerilog Class Hierarchy View

Tue, 18 Jun 2019 00:00:00 +0000

Configure include paths in Sigasi Visual HDL for Eclipse

Thu, 21 Mar 2019 00:00:00 +0000

Quick access to your design environment

Wed, 12 Dec 2018 00:00:00 +0000

Suppress warnings from within your code

Wed, 12 Dec 2018 00:00:00 +0000

Hover (aka Tooltips) for VHDL and SystemVerilog

Tue, 11 Sep 2018 00:00:00 +0000

Naming Conventions for VHDL and SystemVerilog

Tue, 11 Sep 2018 00:00:00 +0000

Block Diagrams for SystemVerilog code

Tue, 26 Jun 2018 00:00:00 +0000

The Block Diagrams View is documented here. The Graphical Config File is documented here.

The Hierarchy View for SystemVerilog code

Tue, 26 Jun 2018 00:00:00 +0000

The Hierarchy View is documented here.

Autocompletes for Verilog and SystemVerilog defines and includes

Wed, 20 Jun 2018 00:00:00 +0000

The Preprocessor View is documented here.

Graphical representation of SystemVerilog State Machines

Wed, 20 Jun 2018 00:00:00 +0000

The State Machine View is documented here.

Making sense of HDL Verification Methodologies

Fri, 03 Feb 2017 00:00:00 +0000

In the last decade a lot has changed in the field of digital hardware design verification. To cope with the increasing complexity of designs, the industry needed better solutions to test hardware. A lot of novel solutions were developed. Some of them have became very successful and some are already obsolete. This can be very confusing for engineers who are new to this field.

SystemVerilog IEEE 1800-2012 Grammar

Fri, 11 Nov 2016 00:00:00 +0000

Copyright The IEEE Standards publication(s) (“Document”) is approved by the IEEE Standards Association (“IEEE-SA”) Standards Board and is published in accordance with established IEEE-SA Standards Board bylaws and operations procedures.

Smart Indentation for Verilog

Fri, 15 Jan 2016 00:00:00 +0000

You can find more info in the manual.