Testbench generation with Wavedrom

Tue, 20 Sep 2016 00:00:00 +0000

Intro

Last academic year (2015-2016), Winand Seldeslachts joined Sigasi to work on his masters thesis. For his thesis he investigated a new way to test VHDL code by extending Wavedrom. Wavedrom is a simple, textual language that is used to describe and visualized timing diagrams. Winand investigated how Wavedrom files could be used to generate input for VHDL testbenches.

Thesis on Sigasi

Testbench generation with Wavedrom

Intro