UVVM on Sigasi

Scale Your Verification Without Losing Control

Wed, 28 Jan 2026 00:00:00 +0000

Learn how modern verification frameworks and the right tooling help you build scalable, maintainable, and efficient testbenches.

Webinar Survey

Tue, 13 Jan 2026 00:00:00 +0000

Thank you for joining us on our first webinar on October 15th, 2025.

As we haven’t seen you at the Visualization & Navigation Webinar on November 27th and you did not yet register for the Verification Frameworks on January 28th, we would like to get your feedback. Thank you for answering the following questions and helping us improve the webinars.

Keep verification focused on real bugs

Thu, 29 Jan 2026 00:00:00 +0000

Verification capacity isn’t scaling with design complexity. In the latest Wilson Research trend reports referenced here, 87% of FPGA projects reported non-trivial bug escapes, and IC/ASIC first-silicon success was only 14%.

Reduce avoidable RTL churn

Thu, 29 Jan 2026 00:00:00 +0000

Sigasi turns VS Code into a professional HDL engineering workspace for VHDL, SystemVerilog, and mixed-language projects. It provides deterministic, project-aware feedback while engineers write RTL, so teams spend less time on avoidable rework and more time on real design progress.

Done doesn't mean "correct"

Mon, 19 Jan 2026 00:00:00 +0000

If you’re managing chip projects, the hardest part isn’t writing/generating more RTL; it’s predicting verification + debug. This isn’t an “FPGA problem” or an “ASIC problem.” It’s a verification predictability problem.

Verification is eating the schedule

Fri, 12 Dec 2025 00:00:00 +0000

The 2024 Wilson Research Group Functional Verification Trend Reports point to a harsh reality: design complexity is rising faster than verification capacity, and the industry is paying for it in escapes, respins, and delays.

Verification Frameworks - Webinar on demand

Tue, 02 Dec 2025 00:00:00 +0000

On January 28th we presented our first webinar in 2026, in which we showed how Sigasi’s shift-left approach saves you valuable time and money in verification. A must watch for design & verification engineers in both SystemVerilog and VHDL.

Getting started with verification in UVVM

Mon, 01 Sep 2025 00:00:00 +0000

Universal VHDL Verification Methodology (UVVM) is an open-source framework designed to streamline the creation of structured VHDL testbenches, facilitating the verification of FPGA and ASIC designs. It provides a comprehensive library of verification components and utilities to help design teams reduce the effort and complexity involved in writing testbenches. If you are familiar with UVM , UVVM is UVM’s VHDL counterpart.

How to set up the UVVM Library in Sigasi Visual HDL

Mon, 04 Nov 2024 00:00:00 +0000

Introduction

UVVM (Universal VHDL Verification Methodology) is an open-source framework designed to streamline the creation of structured VHDL testbenches, facilitating the verification of FPGA and ASIC designs. It provides a comprehensive library of verification components and utilities to help design teams reduce the effort and complexity involved in writing testbenches.