Verilog on Sigasi

Meet Our Intern Joran De Decker

Fri, 04 Sep 2026 00:00:00 +0000

Meet Joran, born and raised in Belgium: from dead-end diagrams to a documentation feature he’s proud of

Meet Our Intern Ema Filipovska

Thu, 20 Aug 2026 00:00:00 +0000

This is the first post in a new series where we introduce you to some international students who’ve spent their internship building alongside our engineering team. First up: Ema, Macedonian, who wraps up her time at Sigasi at the end of this month.

How to code resets in Verilog

Mon, 04 May 2026 00:00:00 +0000

In digital design, resets are used to bring a circuit into a predefined state after power-up. This article focuses on how to design resets for synchronous digital circuits in Verilog and SystemVerilog.

Verilog Assignments: blocking or non-blocking?

Mon, 27 Oct 2025 00:00:00 +0000

Verilog / SystemVerilog has two different assignment operators. One assignment operator is blocking, the other one non-blocking. In this article, we’ll discuss how they are different and when to use each of them. Note that we’re talking about assignments in procedures (always, initial etc.) only, and not about continuous assignments.

ANSI and Non-ANSI Port Declarations in Verilog

Wed, 02 Aug 2023 00:00:00 +0000

In Verilog, module ports can be declared using one of two styles: ANSI or non-ANSI. This article covers the distinct syntaxes of these two styles, as well as further differences between them.

Sigasi's Software Development Kit Part 2

Mon, 30 May 2022 00:00:00 +0000

In the previous installment of this blog, we talked about why you would want to integrate Sigasi’s SDK into your own product portfolio. To summarize our arguments:

The SDK allows you to offer an editing experience in your own product line that is similar to a full blown IDE.
Developing such capabilities from scratch would be prohibitively expensive.

So, hopefully by now you’re convinced you want to license our SDK … but now what? In this installment, we want to focus on some practical aspects of integrating our SDK. The goal is to make you aware of the (limited) additional work you might be confronted with.

Sigasi's Software Development Kit Part 1

Mon, 25 Apr 2022 00:00:00 +0000

At Sigasi, we build tools to make you more productive. Specifically, we enhance your productivity during chip design with SystemVerilog and VHDL. This is why we create our end-user focussed Sigasi Visual HDL.

Case statements in VHDL and Verilog

Thu, 17 Dec 2020 00:00:00 +0000

In programming languages, case (or switch) statements are used as a conditional statement in which a selection is made based on different values of a particular variable or expression. A general discussion of these statements can be found here .

Actual? Formal? What do they mean?

Wed, 14 Oct 2020 00:00:00 +0000

In this article, we discuss the terms actual and formal. These terms show up in the Language Reference Manual of Verilog and VHDL, and they also show up in some of the error messages in Sigasi Visual HDL. Actuals and formals are short for actual and formal arguments of functions, procedures, entities, modules, etc.

Wildcards in sensitivity lists in VHDL and Verilog

Mon, 28 Sep 2020 00:00:00 +0000

In hardware description languages (HDL), sensitivity lists are used to indicate which events may trigger a VHDL process or Verilog always statement. These trigger events are usually transitions of signals that are inputs of the process or always statement.

Recovering Verilog and SystemVerilog Parser

Fri, 31 Jan 2020 00:00:00 +0000

When you’re writing HDL code, be it in SystemVerilog, Verilog or VHDL, your code is broken or incomplete most of the time. Any regular compiler stops on the first error it encounters and will often only show an obscure error message. At Sigasi, we are convinced productivity and happiness of HDL developers increase when they receive immediate feedback on broken code.

Prefix all signals in an instantiation

Fri, 11 Oct 2019 00:00:00 +0000

When you autocomplete an instantiation using the Sigasi Content Assist, wire or signal names in the port map get a default value that is equal to the port name. In many designs, this can be insufficient. You might need to give the wires/signals in the portmap a prefix so they match the actual wire/signal names in the design.

Fixing Verilog is easy

Mon, 19 Sep 2011 00:00:00 +0000

The example in my previous post “Wasting real time in zero time” has triggered some interesting responses, providing more than enough material for a follow-up post. VHDL designers beware, hardcore Verilog stuff ahead!