Tech Articles
Welcome to the Sigasi tech article collection!
These posts handle various topics related to our technology and its use in your environment. Don’t hesitate to Contact Us with any questions regarding the contents of these articles.
Recent Articles
Verilog Assignments: blocking or non-blocking?
Verilog / SystemVerilog has two different assignment operators. One assignment operator is blocking, the other one non-blocking. In this article, we’ll discuss how they are different and when to use each of them. Note that we’re talking about assignments in procedures (always, initial etc.) only, and not about continuous assignments.
2025-10-27
Setting up a VUnit project in VS Code
This article explains how to set up VUnit with the new Sigasi Project format. This method uses a scripted target to integrate VUnit’s compilation flow into Sigasi Visual HDL.
2025-10-17
Getting started with verification in UVVM
Universal VHDL Verification Methodology (UVVM) is an open-source framework designed to streamline the creation of structured VHDL testbenches, facilitating the verification of FPGA and ASIC designs. It provides a comprehensive library of verification components and utilities to help design teams reduce the effort and complexity involved in writing testbenches. If you are familiar with UVM , UVVM is UVM’s VHDL counterpart.
2025-09-22