A few weeks ago, a friend of mine talked about using a seven-segment display in a VHDL lab in his university .
Of course, he wanted his students to simulate before they synthesize. I thought it would be nice to have a module that can emulate a this a seven-segment display as ASCII-art.
I created this module in about an hour and after some more minor modifications, I decided to publish it for everybody to use.
You can download the VHDL source code for this project and use it under the conditions of the BSD License . (contact us if you need a different license.)
See also
- Why can't HDL designers live without block selection mode? (opinion)
- Four (and a half) ways to write VHDL instantiations (legacy)
- Insights into FSM Design Practice (blog post)
- Signal Assignments in VHDL: with/select, when/else and case (blog post)
- How to set up the UVM Library in Sigasi Visual HDL (knowledge)