Tech Articles on Sigasi

Verilog Assignments: blocking or non-blocking?

Mon, 27 Oct 2025 00:00:00 +0000

Verilog / SystemVerilog has two different assignment operators. One assignment operator is blocking, the other one non-blocking. In this article, we’ll discuss how they are different and when to use each of them. Note that we’re talking about assignments in procedures (always, initial etc.) only, and not about continuous assignments.

Sigasi Visual HDL Preview (2026.1)

Fri, 17 Oct 2025 00:00:00 +0000

For users who want early access to the features and bug fixes of upcoming Sigasi Visual HDL releases, we have set up an extra release channel called Sigasi Preview.

The Sigasi Preview release channel offers more frequent releases than the official releases. This page gives an introduction to the most important changes.

Setting up a VUnit project in VS Code

Thu, 09 Oct 2025 00:00:00 +0000

This article explains how to set up VUnit with the new Sigasi Project format. This method uses a scripted target to integrate VUnit’s compilation flow into Sigasi Visual HDL.

Getting started with verification in UVVM

Mon, 01 Sep 2025 00:00:00 +0000

Universal VHDL Verification Methodology (UVVM) is an open-source framework designed to streamline the creation of structured VHDL testbenches, facilitating the verification of FPGA and ASIC designs. It provides a comprehensive library of verification components and utilities to help design teams reduce the effort and complexity involved in writing testbenches. If you are familiar with UVM , UVVM is UVM’s VHDL counterpart.

Insights into FSM Design Practice

Thu, 31 Jul 2025 00:00:00 +0000

Introduction

This article starts with elaborating the necessity for rigor FSM design and its key objectives. It provides exemplary implementations of good practices. Finally, it goes over a step by step example of building an FSM with the help of Sigasi Visual HDL (SVH) on VS Code.

Signal Assignments in VHDL: with/select, when/else and case

Thu, 05 Jun 2025 00:00:00 +0000

VHDL provides several ways to assign values to a signal based on the value of another. Most of the time, there’s more than one valid approach, and each has its advantages depending on clarity, maintainability, and tool support. This guide covers three primary idioms: selected signal assignment (with/select), conditional signal assignment (when/else), and case statements inside processes.
VHDL-2008 introduced a 4th idiom: pattern matching in case statements. We’ll conclude with practical considerations for using the right construct.

Better call SAL

Wed, 07 Aug 2024 00:00:00 +0000

More than a year ago, we published a blog post discussing the effectiveness of using GitHub Copilot in combination with Sigasi (see original post). Since then, we’ve integrated our own AI tool, SAL (Sigasi AI layer), into Sigasi® Visual HDL™ (SVH™), making it a great time to revisit the topic. In this article, we used SAL in combination with various language models to evaluate its strengths and weaknesses.

Exploring GitHub Copilot

Mon, 04 Dec 2023 00:00:00 +0000

Two years ago, GitHub Copilot was released as an AI-powered coding assistant. Since then, it has been widely used by software developers. So far, it has delivered very good results with programming languages such as C++ or Python. We decided to run some experiments to see how it would perform with hardware description languages. Here is what we have found out.

Rapid Waveforms with GTKWave

Mon, 16 Oct 2023 00:00:00 +0000

My name is Felix, and I’ve been working at Sigasi for about a year and a half at the time of writing. My background is in software development and mathematics, so I took a VHDL course a year ago, together with some other colleagues, to get a better feel for the context I’m now working in.

ANSI and Non-ANSI Port Declarations in Verilog

Wed, 02 Aug 2023 00:00:00 +0000

In Verilog, module ports can be declared using one of two styles: ANSI or non-ANSI. This article covers the distinct syntaxes of these two styles, as well as further differences between them.

Using VUnit for Real

Wed, 26 Apr 2023 00:00:00 +0000

VUnit is an open-source unit testing framework for VHDL and SystemVerilog that helps write and execute tests. VUnit scans your projects for unit tests (aka test benches), runs them with your favorite simulator, and reports the results. This automation helps run tests (more) frequently and iterate faster.

Using VUnit in a GitLab CI Verification Environment

Wed, 14 Dec 2022 00:00:00 +0000

Introduction

Continuous Integration (CI) and Continuous Deployment (CD) are getting more and more important in today’s development processes, especially when working agile/lean by using DevOps principles. It helps to find errors earlier, makes designs more reliable, and in the end it takes pressure off the FPGA developers who too often have really long days and nights to meet deadlines.

VUnit: managing input files and compile order

Thu, 29 Sep 2022 00:00:00 +0000

Some time ago, while preparing for an earlier article on VUnit and UVM, a warning message in a VUnit run caught my attention.

Compiling into lib: vhdl_adder_tb.sv passed
WARNING VCP2515 "Undefined module: vhdl_adder was used. Port connection rules will not be checked
 at such instantiations." ".../vhdl_adder_tb.sv" 20 6
Compiling into lib: vhdl_adder.vhd passed

The tests themselves were running nicely, but hey! VUnit compiles the testbench before the relevant design under test (DUT) and the compiler complains that the DUT is not available when compiling the testbench. Wasn’t VUnit supposed to figure out the compile order by itself?

VHDL 2019: Conditional Analysis

Tue, 02 Aug 2022 00:00:00 +0000

If you are writing universal, portable VHDL code, be it a design that targets multiple chip families, or a library that should work with multiple simulators, you may have noticed that it can be quite challenging to make things work everywhere. Different vendors provide their own macros and IPs, simulators provide their own utility libraries, tools support different VHDL attributes. Your code may be treated differently or even fail to compile if it uses language features that are not supported by one of the tools.

Running UVM tests in VUnit

Tue, 28 Jun 2022 00:00:00 +0000

VUnit and UVM are two increasingly popular standards in the field of HDL verification.

VUnit, as the name suggests, is primarily intended for unit testing. Compared to system tests, unit tests are typically small, and VUnit test are written by designers or verification engineers in the same HDL as the design. VUnit supports both VHDL and SystemVerilog for designs and testbenches.

7 reasons why you should try out our VS Code extension, number 4 will blow your mind 👀

Mon, 16 May 2022 00:00:00 +0000

Sigasi is always trying to innovate in the world of digital design. We have been developing and improving our Eclipse-based flagship product: Sigasi Visual HDL. This has improved the productivity of many digital designers around the world, making them focus on what’s really important: designing.

Sigasi Visual HDL in your design flow, and vice versa

Fri, 22 Oct 2021 00:00:00 +0000

The challenges in a world of ever increasing complexity of (integrated) electronic circuits are often addressed by greater automation, advanced design processes and more sophisticated tools. Even though these help to cope with more complex designs, they also introduce more complexity in the design flow itself. Running the sequence of design automation tools that are necessary to accomplish the design is in itself a challenge that the designer must handle.

Build systems for HDL projects

Tue, 04 May 2021 00:00:00 +0000

Introduction

For a long time, software developers have enjoyed build systems to help them build their code. These build systems keep track of dependencies and call the appropriate tools to run the design flow or parts thereof. In this article, we try to give an overview of currently available build tools for VHDL and (System)Verilog projects.

Case statements in VHDL and (System)Verilog

Thu, 17 Dec 2020 00:00:00 +0000

In programming languages, case (or switch) statements are used as a conditional statement in which a selection is made based on different values of a particular variable or expression. A general discussion of these statements can be found here .

Actual? Formal? What do they mean?

Wed, 14 Oct 2020 00:00:00 +0000

In this article, we discuss the terms actual and formal. These terms show up in the Language Reference Manual of VHDL and (System)Verilog, and they also show up in some of the error messages in Sigasi Visual HDL. Actuals and formals are short for actual and formal arguments of functions, procedures, entities, modules…

Wildcards in sensitivity lists in VHDL and Verilog

Mon, 28 Sep 2020 00:00:00 +0000

In hardware description languages (HDL), sensitivity lists are used to indicate which events may trigger a VHDL process or (System)Verilog always statement. These trigger events are usually transitions of signals that are inputs of the process or always statement.

How to code reset in a synchronous VHDL process

Tue, 11 Aug 2020 00:00:00 +0000

In digital design, resets are used to bring a circuit into a predefined state after power-up. This article focuses on how to design resets for synchronous digital circuits in VHDL. The concepts discussed in this article are equally valid in other design languages e.g. Verilog.

VHDL 2019: Usability and APIs

Thu, 18 Jun 2020 00:00:00 +0000

In this fourth and last article in our series about VHDL 2019, we discuss some smaller usability improvements. The new and improved APIs are also mentioned. You can read the third part here.

VHDL 2019: Enhanced generic types

Tue, 16 Jun 2020 00:00:00 +0000

This is the third article in our series about VHDL 2019. In this article the enhanced generic types are discussed. You can read the second part here.

Enhanced generic types

VHDL 2019 improves generic types and subprograms. In VHDL 2008 generic types were introduced, these generic types can be bound to any type. In addition to the generic type, a number of generic operations can be provided with the type. For example:

VHDL 2019: Interfaces

Thu, 11 Jun 2020 00:00:00 +0000

This is the second article in our series about VHDL 2019. In this article we look at the new ability to cleanly express interfaces. You can read the first part here.

What's new in VHDL 2019?

Tue, 09 Jun 2020 00:00:00 +0000

Introduction

This article is the first in a series of articles that are taken from the talk VHDL 2018: New and Noteworthy (slides ). This talk was given by our colleague Lieven Lemiengre at DVCON 2018. Since the new VHDL standard was approved and published in 2019, all references to 2018 from the talk have been replaced by 2019 in this series of articles.

Records in VHDL: Initialization and Constraining unconstrained fields

Tue, 31 Mar 2020 00:00:00 +0000

In VHDL, records help the designer organize data that belongs together. By using records, VHDL code will be easier to understand and maintain. This article highlights a couple of slightly more advanced aspects of record types in VHDL, namely how to use record constants, and how to use unconstrained data types as fields in records. We’ll see that, apart from some particular syntax, records are fairly easy to use after all.

Finite State Machine (FSM) encoding in VHDL: binary, one-hot, and others

Fri, 06 Mar 2020 00:00:00 +0000

State diagram in Sigasi Visual HDL Professional

In VHDL, Finite State Machines (FSMs) can be written in various ways. This article addresses the encoding of, and the data types used, for the state register. The encoding of the states of an FSM affects its performance in terms of speed, resource usage (registers, logic) and potentially power consumption. As we will see, enumerated datatypes are preferred for clarity and easy of maintenance.

Recovering Verilog and SystemVerilog Parser

Fri, 31 Jan 2020 00:00:00 +0000

When you’re writing HDL code, be it in SystemVerilog, Verilog or VHDL, your code is broken or incomplete most of the time. Any regular compiler stops on the first error it encounters and will often only show an obscure error message. At Sigasi, we are convinced productivity and happiness of HDL developers increase when they receive immediate feedback on broken code.

Register Description Language SystemRDL 2.0

Tue, 23 Apr 2019 00:00:00 +0000

Get the full Language Reference Manual, free of charge, at https://www.accellera.org/downloads/standards/systemrdl

Sigasi has created this browsable version of the grammar, hoping that it would be useful to you, but without any warranty whatsoever.

Portable Test and Stimulus Standard Version 1.0

Wed, 27 Jun 2018 00:00:00 +0000

Get the full Language Reference Manual, free of charge, at http://www.accellera.org/downloads/standards/portable-stimulus

Sigasi has created this browsable version of the grammar, hoping that it would be useful to you, but without any warranty whatsoever.

Using the util package from Modelsim with VHDL 2008

Mon, 15 Jan 2018 00:00:00 +0000

The util package that comes with Modelsim in the mti_util.vhd file includes an enumerated type forcetype that is defined as:

 VHDL
 
type forcetype is (default, deposit, drive, freeze);

In VHDL 2008, default is a new keyword. This causes problems in VHDL 2008 projects that use the util package. Still, Sigasi Visual HDL allows to use the modelsim_lib.util package in VHDL 2008 projects.

Array size mismatches with generic port widths

Tue, 09 Jan 2018 00:00:00 +0000

Customer question

On a regular basis we receive questions from customers about Incorrect array size warnings or errors.

VHDL IEEE 1076-2017 Grammar

Thu, 27 Jul 2017 00:00:00 +0000

Based on the VHDL 2017 Standard Draft

This document is copyrighted by the IEEE. It is made available for a wide variety of both public and private uses. These include both use, by reference, in laws and regulations, and use in private self-regulation, standardization, and the promotion of engineering practices and methods. By making this document available for use and adoption by public authorities and private users, the IEEE does not waive any rights in copyright to this document.

Property Specification Language (PSL) Grammar

Thu, 02 Feb 2017 00:00:00 +0000

IEEE Std 1850-2010

This document is copyrighted by the IEEE. It is made available for a wide variety of both public and private uses. These include both use, by reference, in laws and regulations, and use in private self-regulation, standardization, and the promotion of engineering practices and methods. By making this document available for use and adoption by public authorities and private users, the IEEE does not waive any rights in copyright to this document.

VHDL file encoding

Wed, 25 Jan 2017 00:00:00 +0000

Introduction

I have been using VHDL for almost two decades and never wondered how I should save my VHDL files. Because of my software engineering background, I always use UTF-8 as the default character or file encoding and never had any issues with it.

SystemVerilog IEEE 1800-2012 Grammar

Fri, 11 Nov 2016 00:00:00 +0000

Copyright The IEEE Standards publication(s) (“Document”) is approved by the IEEE Standards Association (“IEEE-SA”) Standards Board and is published in accordance with established IEEE-SA Standards Board bylaws and operations procedures.

VHDL IEEE 1076-2008 Grammar

Thu, 22 Sep 2016 00:00:00 +0000

VHDL Assert and Report

Mon, 02 Feb 2015 00:00:00 +0000

How can you check invariants in VHDL? How can you write information to the console? That is what the VHDL assert statement and report statement are for!

The basic syntax of a report statements in VHDL is:

Name shadowing in VHDL

Mon, 26 Jan 2015 00:00:00 +0000

Like many other languages, it is possible in VHDL to perform name scoping. This happens if you declare a new object in a nested scope that reuses the name of an object that was already declared. This is not an error in VHDL, but it can be confusing and it can cause errors. In general, I would advice against name scoping unless you have a very good reason. Even then, it would be best if you document (comment) your code so that everybody understands what is going on.

Use environment variables to set up External Compilers

Fri, 24 Oct 2014 00:00:00 +0000

Some teams have a setup where environment variables are automatically set by scripts, to reflect the paths of the correct version of simulators and synthesis tools. In cases like this, it is better to configure Sigasi External Compilers to use these environment variables instead of absolute paths to find the installation path of external compilers.

To "to" or to "downto"... Ranges in VHDL

Fri, 05 Sep 2014 00:00:00 +0000

Most VHDL designers write ‘something downto something’ in their code all the time. But what does this downto actually mean? And what is the difference with to?

The keywords downto and to specify the direction of ranges in VHDL. downto is descending (going down); to is ascending (going up).

How much time is spent on writing documentation versus developing RTL code?

Wed, 27 Nov 2013 00:00:00 +0000

Estimation of time for technical documentation and software development

Estimating software development schedules is a skill. The programmer who is going to do the work can figure out what steps they will need to take to implement that feature. And only the programmer can estimate how long each one will take. The nature of software development is that things which seem simple are often surprisingly complicated when we think about all the details. Attempting to estimate a feature before we’ve figured out how the feature is going to work, in detail, can’t possibly work, even if we multiply our best guess by three, because our “best guess” is based on very little in the way of facts. One of the most painful questions that developers are faced with is estimation and justification of time required for technical documentation development. Documentation developers need a methodology to provide a more or less precise and, most importantly, well-grounded estimation of documentation development time, already at the problem definition stage.

Why you need good documentation for your VHDL and Verilog code

Sun, 10 Nov 2013 00:00:00 +0000

In this blog series, guest blogger Smrita talks about the need for documentation for complex RTL designs.

In engineering, technical documentation refers to any type of documentation that describes handling, functionality and architecture of a technical product or a product under development or use. The intended recipient for product technical documentation is both the (proficient) end user as well as the administrator, service or maintenance technician. In contrast to a mere “cookbook” manual, technical documentation aims at providing enough information for a user to understand inner and outer dependencies of the product at hand. The technical documentation is intended to help the maintainers of the system (the people who need to keep the system running smoothly, fix problems, etc.) The maintainers are usually technical people, who need to know exactly how the system works .

"Use" and "Library" in VHDL

Mon, 09 Sep 2013 00:00:00 +0000

Beginning VHDL engineers, and advanced engineers too, can get confused about the exact scope of a use clause and a library clause in VHDL. They usually show up at the top of a file, which would make you think that they are visible in the entire file. Unfortunately, the truth is a bit more complex.

Recovering VHDL Parser

Fri, 21 Sep 2012 00:00:00 +0000

It is useful to analyze code that is only partly finished, code that still has errors in it. Analyzing broken code helps people understand, improve and complete the code. In order to perform such an analysis, you need a parser that recovers after it encounters an error. In the world of hardware design, hardly any recovering parsers exist and engineers are left out in the cold. All but a few EDA tools fail miserably at parsing incorrect VHDL code.

Three mistakes, three error markers

Fri, 21 Sep 2012 00:00:00 +0000

Ideally, if you make three mistakes in VHDL, you want to see three error markers. Here is a small example.

A traditional VHDL compiler gives only one error message. You will have to fix this error and start the compiler again before you can find the next error. This takes extra time and you need all of your time you to work on complex design problems that you are dealing with.

Dead code

Wed, 05 Sep 2012 00:00:00 +0000

A hardware design project will often contain code that does nothing. Still, there might be a good reason to have this code. Here are some guidelines to determine if this dead code is useful or not:

Deprecated IEEE Libraries

Tue, 15 May 2012 00:00:00 +0000

What are deprecated IEEE libraries?

Don’t use ieee.std_logic_unsigned and similar libraries because they are not standardized. Instead, use ieee.numeric_std.all.

Clock edge detection

Mon, 09 Apr 2012 00:00:00 +0000

There are two largely accepted ways to detect clock edges, and many style books prescribe or prefer one over the other. Let’s investigate.

This article deals with edge detection in synthesizable code, not with behavioral code as found in test benches and behavioral models.

Advanced VHDL Configurations: Tying a component to an unrelated entity

Thu, 22 Mar 2012 00:00:00 +0000

Usually, people use VHDL configurations to select a given architecture for their component, or even to set generics that were not set in the instantiation. But you can also do more advanced stuff with configurations: you can tie a component to a completely unrelated entity. You can even re-wire the signals!

The scope of VHDL use clauses and VHDL library clauses

Wed, 14 Dec 2011 00:00:00 +0000

When I first learned VHDL, I bumped in to quite a few language quirks. Here is one thing that I learned the hard way: the scope of VHDL use clauses.

VHDL case statements can do without the "others"

Mon, 24 Oct 2011 00:00:00 +0000

I was talking to some engineering students the other day, as they were doing a VHDL lab. I noticed a VHDL case statement for state machine with named states (enumerated data type). All states were handled in their VHDL case statement, and still they put an others section in their code. I had a hard time explaining that this clause was useless. The students mumbled something about their professor eating them alive if they’d forget the others and problems with uninitialized stated and high-impedance state. As you might know, these concepts are related to the std_ulogic and std_logic type, but not to enumerated types.

Package and Package Body: in the same file or in separate files?

Fri, 22 Jul 2011 00:00:00 +0000

Some coding guidelines require that a package and its body should be in the same file. Other guidelines require two separate files, often with rules about the filenames. What is the reason for this?

List of known VHDL metacomment pragma's

Thu, 28 Apr 2011 00:00:00 +0000

Following up on a previous post, VHDL Pragmas, this is an incomplete list of supported VHDL pragmas, organized by vendor.

As an introduction, most pragmas have the following structure:

VHDL

-- trigger directive

where trigger is a keyword such as pragma or synthesis, and the directive is a special compiler directive. Many tools support several triggers, each with identical meaning.

VHDL Pragmas

Tue, 05 Apr 2011 00:00:00 +0000

In VHDL, some tools support so-called compiler directives. A compiler directive, or pragma is additional information that you give to the VHDL compiler (the simulator or synthesis tool). While your directive has no influence on the VHDL code itself, it changes the behavior. The IEEE, in their VHDL RTL standard, defines a pragma as A generic term used to deﬁne a construct with no predeﬁned language semantics that inﬂuences how a synthesis tool will synthesize VHDL code into an equivalent hardware representation.