Every line of HDL, understood and validated. No matter who writes it.

Sigasi Visual HDL builds a semantic model of your whole project, across SystemVerilog, Verilog, and VHDL. It reports errors as the code is written, by you or your coding agent, before any tool runs, and shows you the design as hierarchy, block diagrams, and state machines. You stay in control of what moves forward.

Try it in this interactive demo: pick a feature and watch it run on real HDL code.

Want to run it on your own code?

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Built for professional ASIC and FPGA teams

SystemVerilog
Verilog
VHDL
Mixed-language
VS Code

Your code is part of a project. Your tools should understand it.

A design is more than the single file you are editing. Sigasi builds a semantic model of your whole HDL project, including types, scopes, libraries, interfaces, hierarchies, and dependencies. That shared context powers analysis, navigation, visualization, and agent feedback.

Project-wide context

Follow relationships across files, libraries, and languages.

Feedback at coding speed

Find semantic issues while you develop, instead of downstream.

One shared engine

Use the same foundational semantic models in your workspace, automation, and AI.

Built around the work engineers actually do.

From your first edit to a reviewed handoff: keep the code, project context, and engineering feedback connected.

01 / Analyze and lint

Catch issues while you write RTL.

Sigasi checks your RTL against the whole project, not one file at a time. As you type, it flags vector width mismatches in assignments and port maps, implicit nets, incomplete sensitivity lists and reset branches, inconsistent clock edges, duplicate case choices, and signals that are never read or never written. Many problems come with a quick fix, and you set the severity and parameters of most rules.

Widths, types, and port connections across files
Clocks, resets, sensitivity lists, and dead code
Naming conventions, plus rules mapped to STARC and DO-254

Explore linting

02 / Navigate and refactor

Follow the design, not a trail of files.

Jump to declarations and references, inspect symbols, and navigate through design and class hierarchies. Use language-aware editing, formatting, and rename refactoring to make everyday changes. Cut down on false positives with deterministic algorithms, not heuristics.

Definitions, references, and hover information
Design hierarchy, class hierarchy, and net search
Autocomplete, formatting, and rename refactoring

Explore editing and navigation

03 / Visualize the design

See how the pieces fit together.

Explore block diagrams, state machines, and dependency graphs generated from your source. Flip between visual views and HDL to understand unfamiliar designs and support reviews with more than simple text diffs. When a change set is too large to read line by line, the hierarchy, the connections, and the state machines proof to you whether the design is still the one you intended.

Block diagrams linked to and rendered from source
State machine diagrams and transition views
Project and file dependency views

Explore design visualization

04 / Build verification code

Bring structure to your testbench.

Work with verification code as part of the engineering project. Inspect UVM topology, navigate component relationships, visualize and run VUnit tests, and catch methodology-specific issues before they interrupt a simulation run.

UVM-specific linting
UVM topology and diagrams
VUnit integration and test execution

Explore UVM support

05 / Configure real projects

Start with the project you already have.

Represent existing sources, libraries, and dependencies in a project setup shared amongst your team. Modular Projects support Vivado, VUnit and custom scripted workflows, cutting down on duplicated configurations and getting you started quickly.

SystemVerilog, Verilog, and VHDL together
Library mappings, include paths, and dependencies
Modular Projects and supported project imports

Explore project setup

06 / Automate and document

Carry project knowledge into your workflow.

Use the Sigasi CLI to validate projects, export reports, and generate documentation in automated workflows. Share source-derived design information and compilation data with the people and tools that take the project forward.

CLI analysis and machine-readable linting
Source-derived documentation and diagrams
Compilation order and recipe export

Explore CLI automation

Your testbench deserves the same engineering depth as your RTL.

Verification engineers need to understand class hierarchies, component relationships, and project configuration as well as source code. Sigasi combines language-aware navigation with UVM-specific analysis and visual views to make complex verification environments easier to inspect and maintain.

UVM-specific linting, topology, and diagrams support SystemVerilog verification. VUnit integration connects test execution. Explore workflows with OSVVM, UVVM, and cocotb, and confirm the configuration needed for your environment.

Watch the UVM walkthrough

Sigasi supports verification development, but it does not replace simulation, formal verification, coverage analysis, or sign-off.

Sigasi Visual HDL in VS Code with the class hierarchy and design hierarchy of a UVM testbench, its UVM diagram, and a UVM linting hover in the editor

AI proposes. Sigasi checks. You decide.

Give your coding agent access to a project-aware linter instead of having it spend tokens to evaluate its own output. Sigasi exposes its semantic engine through MCP and CLI, so an agent can pull file and project diagnostics, project context, or search for symbols, act on what it finds, and check again. The final code can then be formatted through MCP or CLI. The agent is checked in real-time against the same semantic model and analysis used in your workspace and exposed via your CI/CD. You remain in control: inspect the resulting code and design relationships before deciding what lands.

Explore the agent integration

AI integration is optional. Making tools available does not guarantee an agent will call them. Configure your workflow and review process accordingly.

The agent + deterministic feedback loop

Your coding agent Proposes and modifies HDL.

Sigasi Provides context and reports issues

The engineer remains accountable

Inspect the code, understand the design, and decide what moves forward.

Fix the setup. Don’t touch correct RTL.

See Copilot use Sigasi diagnostics to find the missing include directories in a UVM testbench and fix the project configuration instead of rewriting HDL.

Watch the real workflow

Add engineering context. Keep your existing flow.

Use Sigasi alongside the editors, repositories, simulators, build scripts, and CI systems your team already relies on. Start with the integration that solves today’s problem, then extend the workflow as needed.

Example / machine-readable project check

sigasi-cli verify --json --fail-on-error ./project

Example CLI invocation. Configure the project and appropriate license before use.

Integration routes and scope

Workspace

VS Code Language-aware HDL development, navigation, and visual review.

Coding agents

MCP and CLI Project context and diagnostics for agent workflows.

Project setup

Scripted imports Quickly get set up by importing existing build scripts, Vivado, or VUnit projects.

Automation

CLI and CI reporting Machine-readable results and configurable failure thresholds.

Downstream tools

Compilation order and recipes Drive downstream toolchains through exported project information.

Keep analysis local. Make team rules explicit.

Sigasi performs semantic analysis on your workstation or within your company-controlled environment. Apply configured coding rules and share project settings to support consistent engineering practices.

Commercial Sigasi telemetry is optional. Source code is never uploaded.
A connected AI agent’s data handling depends on its own provider and configuration.
Coding-rule checks support your workflow towards compliance of designs to industry standards.

Review telemetry and deployment details

See Sigasi on real engineering work.

Want to see what using Sigasi is really like? Explore screencasts on specific topics before requesting a trial. See how Sigasi handles source code, verification environments, and agent-driven changes.

RTL quality Find issues earlier See project-aware linting in the editing workflow. Watch screencast

Verification Explore a UVM environment See topology and verification relationships in context. Watch screencast

AI workflows Fix a missing dependency Watch an agent act on deterministic project diagnostics. Watch screencast

Choose the edition that fits your workflow.

Start with the engineering capabilities your team needs, then add visualization, verification support, and automation as your workflow requires.

Designer

Everyday HDL development

Semantic analysis, linting, navigation, and language-aware editing for professional RTL work.

Evaluate Designer

Professional

Deeper design understanding

Extend development with graphical views and verification-oriented capabilities.

Evaluate Professional

Enterprise

Team automation and CI

Bring the shared semantic engine to the command-line and automated engineering workflows.

Evaluate Enterprise

Honest answers. to engineering questions.

Find more in-depth technical information and hands-on examples in the product manual.

Do I need to use AI to benefit from Sigasi?

No. Semantic analysis, linting, navigation, refactoring, and visualization support engineers working directly with HDL. Agent integration simply exposes the same project intelligence in an alternative way.

Can I use SystemVerilog and VHDL in the same project?

Sigasi supports SystemVerilog, Verilog, VHDL, and mixed-language projects. Configure the relevant source files, libraries, and dependencies so analysis reflects your design.

Does Sigasi replace my simulator or verification tools?

No. Sigasi helps identify issues and understand designs earlier. Simulation, formal verification, synthesis, coverage, and sign-off remain part of the downstream engineering flow.

Is my HDL uploaded for Sigasi analysis?

Sigasi semantic analysis runs locally. We suggest to review Sigasi’s telemetry settings separately and assess the data handling of any third-party editor extensions or connected AI agents. Regardless of the telemetry settings, Sigasi Visual HDL never transmits any source code.

Can we use Sigasi outside the editor?

The Sigasi CLI supports headless project analysis, reporting, and other automated tasks with an Enterprise and CI license. See the current licensing and CLI documentation for the intended deployment.

How should our team evaluate it?

Request a commercial trial and use a representative project. Evaluate setup effort, useful diagnostics, navigation, review workflows, and any required agent or CI integration. Team evaluation options are available. Feel free to contact us for a hands-on demo.

Is Community Edition suitable for our commercial project?

Community Edition is for non-commercial use. Request a commercial trial to evaluate Sigasi on company projects and confirm the appropriate edition for your team.

Bring your project. See the difference.

Evaluate Sigasi Visual HDL on a representative FPGA or ASIC project. Explore the diagnostics, navigation, visualization, and integrations that matter to your team.

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Your next evaluation

Bring a representative FPGA or ASIC project

Explore useful diagnostics
Navigate and understand the design
Evaluate your agent and CI workflows