Sigasi® Visual HDL™ (SVH™) is an HDL platform for VHDL and SystemVerilog that gives hardware designers and verification engineers better insight during the design process.
SVH enables users to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. It does so by standardizing the concept of an HDL design project, shifting simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation.
You can try out the completely free-of-charge Community Edition for non-commercial and evaluation purposes. Just download it from the VS Code marketplace and have fun!
